Method for programming multi-level cell

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185030

Reexamination Certificate

active

07145809

ABSTRACT:
A method for programming a multi-level cell (MLC) is disclosed. First, a memory cell with a first storage position and a second storage position is provided. An erasing step is performed to increase the threshold voltages of the storage positions. Then, a judging step is preformed to compare the first programming state and the second programming state, which are going to be programmed for the first storage position and the second storage position, to select a proper programming step.

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patent: 6292394 (2001-09-01), Cohen et al.
patent: 2001/0004325 (2001-06-01), Choi
patent: 2005/0286312 (2005-12-01), Wu et al.
patent: 2006/0140000 (2006-06-01), Liao et al.
patent: 2006/0146603 (2006-07-01), Kuo et al.
patent: 2006/0146613 (2006-07-01), Lee et al.
“Phines: A Novel Low Power Program/Erase, Small Pitch, 2-Bit per Cell Flash Memory” By Author C.C. Yeh et al. / 2002 IEEE / p. 931-934.

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