Static information storage and retrieval – Floating gate – Particular biasing
Patent
1998-05-27
1999-02-23
Fears, Terrell W.
Static information storage and retrieval
Floating gate
Particular biasing
365218, G11C 1300
Patent
active
058751300
ABSTRACT:
A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) includes a semiconductor substrate, and a plurality of field effect transistor memory cells each having a source, drain, floating gate and control gate formed on the substrate. A controller controls a power source to apply an operational pulse to the drain of a cell, and apply a source to substrate bias voltage to the cell while the operational pulse is being applied thereto, the bias voltage having a value selected to reduce or substantially eliminate leakage current in the cell. The operational pulse can be an overerase correction pulse. In this case, a voltage which is substantially equal to the bias voltage is applied to the control gate for the duration of the overerase correction pulse. The operational pulse can also be a programming pulse. In this case, a voltage which is higher than the bias voltage is applied to the control gate of the selected wordline for the duration of the programming pulse. The bias voltage is preferably applied during both the overerase correction and programming pulses, reducing the power requirements and reducing the background leakage of the cells to a level at which program, read and overerase correction operations can be operatively performed.
REFERENCES:
patent: 5642311 (1997-06-01), Cleveland et al.
Bill Colin S.
Chan Vei-Han
Chen John
Gutala Ravi P.
Haddad Sameer S.
Advanced Micro Devices
Alexander David G.
Fears Terrell W.
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