Method for programming flash EEPROM devices

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39518318, G11C 2900

Patent

active

056217382

ABSTRACT:
An improved method of programming flash EEPROM devices is provided, wherein the time required to write a plurality of data bytes to a flash EEPROM device with verification is substantially reduced. The disclosed method significantly reduces the effects of the settling times on the overall program-verification cycle by performing row verification of the programmed data bytes instead of the byte verification associated with conventional verification operations.

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patent: 4797850 (1989-01-01), Amitai
patent: 4860261 (1989-08-01), Kreifels et al.
patent: 4891791 (1990-01-01), Iijima
patent: 5077738 (1991-12-01), Larsen et al.
patent: 5109361 (1992-04-01), Yim et al.
IEEE International Solid-State Circuits Conference Digest of Technical Papers, Feb. 1989, "A 90ns 100K Erase/Program Cycle Megabit Flash Memory", Virgil Niles Kynett et al., pp. 6-395 through 6-398.
IEEE Spectrum, "Flash memories: the best of two worlds", Dec. 1989, Richard D. Pashley et al., pp. 6-402 through 6-405.
Intel Report, "28F020 2048K (256K.times.8) CMOS Flash Memory", Nov. 1990, pp. 6-81 through 6-108.

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