Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-07-25
2002-10-29
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185180, C365S185110
Reexamination Certificate
active
06473341
ABSTRACT:
TECHNICAL FIELD
The present invention refers to a method for programming EEPROM memory devices with improved reliability, and to a respective EEPROM memory device.
BACKGROUND OF THE INVENTION
As is known, floating gate EEPROM memory cells are programmed (written and/or erased) by the Fowler-Nordheim effect by injecting charges through a thin tunnel oxide region by applying appropriate voltages between the terminals of the cells.
For greater clarity, reference is made to
FIG. 1
, showing a known architecture of an EEPROM memory array
1
belonging to a memory device
10
. The memory array
1
comprises a plurality of cells
2
arranged on rows and columns and each formed by a memory transistor
3
and selection transistor
4
. The cells
2
are connected in groups so as to form memory bytes (each comprising, for example, eight cells
2
). In detail, the control gate terminals of the memory transistors
3
of the cells
2
belonging to a same byte are connected, by a respective gate line
5
, to a source terminal of a respective byte enabling transistor
6
; the source terminals of all memory transistors
3
are connected to a common source line S by local source lines
8
a
and source connection lines
8
b
. The drain terminal of each memory transistor
3
is connected to the source terminal of the respective selection transistor
4
. The gate terminals of the selection transistors
4
of the cells
2
arranged on a same row are connected to a same word line
15
. The drain terminals of the selection transistors
4
of the cells
2
arranged on a same column are connected to a same bit line
16
. The drain terminals of the byte enabling transistors
6
arranged on a same column are connected to a same control gate line
17
; and the gate terminals of the byte enabling transistors
6
arranged on a same row are connected to the same word line
15
connected to the selection transistors
4
in the same byte.
FIG. 1
shows only one portion of the memory array
1
corresponding to four complete bytes and part of another two bytes;
FIG. 1
shows two word lines
15
, indicated by WLm and WLm+1, two bit lines
16
of each byte, corresponding to bit
0
and to bit
7
, indicated by BL
0
and BL
7
, and three control gate lines
17
, indicated by CGn, GCn+1, CGn+2.
The word lines
15
generally extend for the entire width of the memory array
1
; the bit lines
16
and control gate lines
17
generally extend for the entire height of the memory array
1
. The local source lines
8
a
are shared by the cells
2
belonging to two adjacent and superposed bytes and are formed preferably by diffusions in the substrate. The source connection lines
8
b
are common to all memory cells belonging to bytes arranged along two adjacent columns. The source connection lines
8
b
are formed preferably by metal lines and extend for the entire height of the memory array
1
.
The typical biasing conditions of the memory array
1
during erase (when electrons are injected into the floating gate regions or positive charges are extracted from the floating gate regions of the memory transistors selected), writing (when electrons are extracted from the floating gate regions or positive charges are injected into the floating gate regions of the memory transistors selected), and reading (when the charge stored in the floating gate regions of the selected memory transistors are sensed) are shown in Table I below.
TABLE I
V
cg
V
d
V
st
V
S
ERASE
V
PP
0 V
≧V
PP
floating
WRITE
0 V
V
PP
≧V
PP
floating
READ
V
R
1 V
V
CC
0 V
In Table I, V
cg
is the voltage applied to the control gate lines
17
, V
d
is the voltage applied to the bit lines
16
, V
st
is the voltage applied to the word lines
15
, and V
S
is the voltage applied to the common source line S. The voltage V
PP
applied during writing may be different from the voltage V
PP
applied during erasing, and the voltage V
CC
is the supply voltage.
During programming, the threshold voltage of the cells is modified with respect to the threshold voltage of the virgin cells (not yet written or erased). Preferably, programming is carried out so that the programming window (the limits of which are defined by the threshold voltage of the written cells and by the threshold voltage of the erased cells) is centered with respect to the threshold voltage of the virgin cells, for minimizing the electric field generated by the charges stored in the floating gate region during the operating life of the memory device, and so increasing the reliability of the memory transistors.
In particular, writing is performed by applying a high voltage to the drain terminal of the addressed cells and leaving the source terminal floating, as represented schematically in
FIG. 1
by a two-position selector
12
which selectively connects the common source line S to ground (during reading) or leaves it floating (during writing and erasing).
Before writing, the threshold voltage of the addressed cells is greater than that of the virgin cells (because of the negative charges stored in the floating gate region). During writing, the threshold voltage becomes smaller than zero, so that the written memory transistors turn on even with the control gate region grounded (depleted memory transistor), as shown in
FIG. 2
, which presents the characteristics of an EEPROM cell during writing and erasing. In particular,
FIG. 2
shows the plot of the threshold voltage versus time in case of write pulses of different amplitude and erase pulses of the same amplitude.
When, during writing, the memory transistor turns on, it conducts current and charges the capacitive load associated to its own source terminal.
Since the source line S is common to the entire memory array
1
, its capacitance is not negligible (for example, it is greater than 1 nF for a 1-Mb memory array), and the source terminal may be considered essentially connected to ground, at least in the transient phase. During this short time interval, the cells that are written more quickly (i.e., the cell or cells that get depleted before the others) conduct a high current. This current is interrupted when the voltage on the source terminal, and hence on the common source line S, is such that all the addressed cells are off, that is &agr;
G
(V
GS
−V
T
)<V
S
, where &agr;
G
is the control gate coupling factor, V
GS
is the voltage drop between the control gate and source regions of the cells, V
T
is the threshold voltage of the addressed cells and V
S
is the source voltage. In practice, during writing, the common source line S is charged by the current of the cells as soon as the latter turn on.
This transient current is undesired, in that it reduces the reliability of the concerned memory cells. In addition, it causes the charge pump circuits used for generating the high write voltage V
PP
to be oversized, in that they must withstand not only the tunnel current (and the current of the drain diode, which is reverse biased), but also the current required for charging the source capacitance.
In addition, during each programming operation, the source voltage increases (up to 5-6 V), thus inducing a possible source disturbance for the entire memory array
1
.
SUMMARY OF THE INVENTION
According to principals of the present invention, a method is provided of programming an EEPROM memory device with an improved technique. An EEPROM memory cell includes floating gate region, a drain region, and a source region. A tunnel current is generated between the floating gate region and the drain terminal of a selected cell. During the generation of the tunneling current, a turn off voltage is supplied to the source region of the selected cell, thus terminating the flow of the tunneling current.
REFERENCES:
patent: 4953129 (1990-08-01), Kobayashi et al.
patent: 5553020 (1996-09-01), Keeney et al.
patent: 5661687 (1997-08-01), Randazzo
patent: 5677873 (1997-10-01), Choi et al.
patent: 5790460 (1998-08-01), Chen et al.
patent: 5949714 (1999-09-01), Hemink et al.
patent: 5978261 (1999-11-01), Tailliet
patent: 0 389 721 (1990-10-01)
Gomiero Enrico
Pio Federico
Carlson David V.
Hoang Huan
Jorgenson Lisa K.
Seed IP Law Group PLLC
STMicroeletronics S.r.l.
LandOfFree
Method for programming EEPROM memory devices with improved... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for programming EEPROM memory devices with improved..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for programming EEPROM memory devices with improved... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2991028