Static information storage and retrieval – Floating gate – Particular biasing
Patent
1991-02-20
1992-07-07
Gossage, Glenn
Static information storage and retrieval
Floating gate
Particular biasing
36518909, 365104, 365226, G11C 1604, G11C 1606
Patent
active
051288958
ABSTRACT:
An improved method for programming a selected memory cell in a virtual ground EPROM array avoids the disturbance of data stored in adjacent memory cells. To avoid disturbance of adjacent cells during programming, the array is efficiently debiased utilizing intercolumn passgates along with slow ramping of the selected column line voltage. The method avoids the disturbance of data stored in adjacent memory cells by first selecting a row line coupled to the selected memory cell and the memory cells adjacent to it. Next, column lines coupled to the source and drain regions of memory cells on one side of the selected memory cell and column lines coupled to the source and drain regions of memory cells on the other side of the selected memory cell are coupled to first and second nodes respectively. The first node is coupled to ground. The potential on the second node is raised at a predetermined rate causing electrons to tunnel onto the floating gate of the selected memory cell, yet in such a manner that the potential across each of the first and second column lines on the other side of the selected memory cell does not disturb the programming state of the adjacent cells.
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Gossage Glenn
Intel Corporation
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