Method for programming a semiconductor memory device

Details Method for programming a semiconductor memory device Method for programming a semiconductor memory device

1993-06-21

1996-12-10

Clawson, Jr., Joseph E.

Static information storage and retrieval

Floating gate

Particular connection

36518509, 36518514, 36518518, 365201, 257319, 257320, G11C 1604

Patent

active

055838103

ABSTRACT:
A programmable EEPROM cell structure consisting in a split-gate structure in series with a coupling capacitor between the floating gate and an additional program gate in order to provide enhanced injection efficiency. The electron injection is controlled by a control gate at the source side. The area of the coupling capacitor is selected with a substantial coupling factor to a high voltage onto the floating gate during programming so as to produce hot-electron injection at the split point in the channel region between the control gate and the floating gate. Submicrosecond programming at a 5 V drain voltage can thereby be achieved.

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IEDM, 1988, R. Kazerounian et al., "5 Volt High Density Poly-Poly Erase Flash EPROM Cell"(p. 436).
European Search Report for corresponding application BE 9100091 bearing the date "08 Oct. 1991".

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