Method for programming a memory structure

Details Method for programming a memory structure Method for programming a memory structure

2008-06-24

2010-12-21

Luu, Pho M (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185130, C365S185140, C365S185150, C365S185260

Reexamination Certificate

active

07855918

ABSTRACT:
A memory structure includes a first memory cell and a second memory cell located at an identical bit line and adjacent to the first memory cell. Each memory cell includes a substrate, a source, a drain, a charge storage device, and a gate. A method for programming the memory structure includes respectively providing a first gate biasing voltage and a second gate biasing voltage to the first memory cell and the second memory cell, boosting the absolute value of a channel voltage of the first memory cell to generate electron and hole pairs at the drain of the second memory cell through gate-induced drain leakage or band-to-band tunneling, and injecting the electron of the generated electron and hole pairs into the charge storage device of the first memory cell to program the first memory cell.

REFERENCES:
patent: 7196930 (2007-03-01), Han et al.
patent: 7460404 (2008-12-01), Dong et al.
patent: 2006/0227613 (2006-10-01), Joo

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