Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-02-12
2002-01-01
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185170, C365S185330
Reexamination Certificate
active
06335881
ABSTRACT:
This application claims priority from Korean Patent Application No.
2000-06443
, filed on Feb. 11, 2000, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
The present invention relates to a semiconductor device and, more particularly, to a method for programming a nonvolatile semiconductor memory device to improve its program time.
BACKGROUND OF THE INVENTION
Recently, demand for semiconductor memory devices that are electrically programmed and erased without refreshing data stored in the memory devices has increased. Also, it is a main trend to increase storage capacity and integration density of semiconductor memory devices thereof. A NAND-type flash memory device, for example, is a nonvolatile semiconductor memory device for providing large capacity and high integration density without refreshing stored data. Since the nonvolatile semiconductor memory devices maintain their data at power-off, they are widely used in applications where power can be suddenly interrupted.
A NAND-type flash memory device is a nonvolatile semiconductor memory device includes electrically erasable programmable read-only memory (EEPROM) cells, which are often referred to as “flash EEPROM cells”. The flash EEPROM cell comprises a cell transistor, which has a semiconductor substrate (or bulk) of a first conductivity type (e.g., P-type), spaced source and drain regions of a second conductivity type (e.g., N-type), a floating gate placed over a channel region between the source and drain regions for storing charges, and a control gate placed over the floating gate.
As well known to those skilled in the art, the NAND-type flash memory device comprises an array of NAND-structured EEPROM cells. A cross-sectional diagram of the array is illustrated in some detail in “Semiconductor Memories: A Handbook of Design, Manufacture, and Application” by Betty Prince, 2
nd
Ed., John Willey & Sons, pp. 698-717 (1991), which is hereby incorporated by reference.
The flash EEPROM cell transistor is programmed or erased by the so-called F-N tunneling mechanism. A rough description of the mechanism is as follows. A cell transistor is erased carried out by applying a ground voltage (0V) to its control gate and a voltage (e.g., 20V), higher than a power supply voltage, to its bulk or substrate. This large voltage difference sets up a strong electric field between the floating gate and the bulk such that electrons on the floating gate are discharged into the bulk. The effect is termed F-N tunneling. A threshold voltage of erased cell transistor shifts into a negative direction (e.g., −3V). This state is defined as data “1” and a flash EEPROM cell having the data “1” a state is called an “on-cell”.
In order to program the cell transistor, a voltage (e.g., 18V) higher than the power supply voltage is applied to its control gate and a ground voltage is applied to its drain and bulk. Under this bias condition, electrons are injected in the floating gate of the cell transistor by the F-N tunneling effect. The threshold voltage of the programmed memory cell shifts into a positive direction (e.g., 1V). This state is defined as data “0” and a flash EEPROM cell having the data “0” a state is called an “off-cell”.
A detailed description of the program operation is as follow. First, a command (e.g., ‘80’h) indicating a sequential data input is provided to a flash memory device having the array of programmed memory cells. An address and data are then sequentially provided to an address buffer circuit and a page buffer circuit. After a data input, a high voltage generating circuit generates a high control gate voltage responsive to a command (e.g., ‘10’h) indicating the start of programming. At the same time, bit lines are set with a power supply voltage (or a program inhibition voltage) or a ground voltage (or a program voltage) according to data loaded in the page buffer circuit. This operation is called “a bit line setup operation”. After the bit line setup operation, the high voltage from the high voltage generating circuit is supplied to a selected word line. This last operation is called “a program operation”. After a predetermined time elapses under the bias condition of the program operation, data from selected cell transistors is read. This operation is called “a verify operation”. If at least one of the selected cell transistors is insufficiently programmed, the above-described programming process, which consists of a subset of the bit line setup operation, the program operation, and the verify operation, is repeated by predetermined number of program loops. with each program loop, the high voltage is increased.
A technique for increasing the high voltage at each program loop iteration is disclosed in IEEE International Solid-State Circuits Conference, 1995, pp.128-129, “
A
3.3
V
32
Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme
,” by Suh, Kang-Deog et al., which is hereby incorporated by reference.
A problem arises when the above-mentioned program method is applied to the NAND-type flash memory device. This problem involves carrying out the program operation before the high voltage reaches a required voltage level. Causing the first program loop to fail. If the first program loop fails, the number of program loops consequently increases thereby increasing program time. Also, a flash EEPROM cell transistor to be programmed at the first program loop is over-programmed at the following program loop due to the initial program fail are because the high voltage applied to a selected word line is increased by a predetermined voltage (e.g., 0.4V) at the following program loop. The result is that operating characteristics of programmed cell transistors are adversely affected.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a flash memory device capable of overcoming the disadvantages and problems associated with prior art flash memory devices. It is another object of the present invention to provide a flash memory device capable of reducing program time.
It is but another object of the present invention to provide a method of programming a flash memory device, that is capable of preventing characteristic of an EEPROM cell degradation.
In order to provide this and other objects, advantages and features according to the present invention, a method of programming a a nonvolatile semiconductor memory device is provided. The nonvolatile semiconductor memory device includes an array of electrically erasable and programmable read-only memory cells (EEPROMs) arranged in a matrix of rows and columns and a page buffer circuit coupled to the array via the columns. The method comprises sequentially loading program data in the page buffer circuit responsive to a first command signal, the first command signal indicating program data input and generating a program voltage responsive to a second command signal, the second command signal indicating programming initiation. EEPROM cells are programmed after the program voltage reaches a predetermined target. Programming the EEPROM cells includes charging the columns with either a program-inhibit voltage or a column program voltage depending on the program data, supplying the program voltage to a selected row to thereby program the EEPROM cells on the selected row, and discharging the rows and columns after charging and supplying. Data is read out from the programmed EEPROM cells after discharging. All of the programmed EEPROM cells are verified to ensure that they are properly programmed. If the EEPROM cells are not properly programmed, programming is repeated until all of the EEPROM cells are properly programmed. After each programming iteration, the program voltage is increased in a stepwise manner.
REFERENCES:
patent: 5953251 (1999-09-01), Caravella
Kim Eun-Cheol
Kim Jong-Hwa
Lam David
Marger & Johnson & McCollom, P.C.
Nelms David
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