Method for profile control of selective metallization

Details Method for profile control of selective metallization Method for profile control of selective metallization

1993-01-25

1995-07-04

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437238, 437245, 437192, H01L 2144

Patent

active

054299870

ABSTRACT:
A method for forming interconnects in an integrated circuit chip which includes a plurality of active devices over which a layer of dielectric material is deposited. The method comprises: (a) depositing a selective nucleating layer on the dielectric layer; (b) depositing a sacrificial layer over the nucleating layer; (c) pattering the sacrificial layer and nucleating layer such that the resulting pattern of the nucleating layer and sacrificial layer is equivalent to the desired pattern of conductive lines; (d) depositing a sidewall guide material over the patterned sacrificial and nucleating layers; (e) forming sidewall guides; (f) removing the sacrificial layer; and (g) depositing conductive material between the sidewall guides and on the nucleating layer. The nucleating layer may comprise titanium nitride, the sacrificial layer may comprise silicon dioxide, the sidewall guide material may comprise silicon nitride, and the conductive material may comprise copper. In another aspect of the invention, a layer of silicon nitride may be provided over the conductive material.

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patent: 5077236 (1991-12-01), Kim
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patent: 5314832 (1994-05-01), Deleonibus
Copper Interconnection with Tungsten Cladding for ULSI, Cho, Kang, Beiley, Wong and Ting 1991 Symposium VLSI Technology, Oiso, Japan pp. 37-40.
Encapsulated Copper Interconnection Devices Using Sidewall Barriers, Gardner, Onuki, Kudoo, Misawa 1991 VMIC Conference Proceedings (IEEE) Jun. 11, 1991 pp. 99-108.

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