Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2001-01-03
2002-11-05
Ho, Hoai (Department: 2818)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S551000
Reexamination Certificate
active
06475919
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a method for producing trenches for manufacturing storage capacitors in DRAM cell configurations.
In known DRAM cell configurations—that is, memory location configurations with dynamic random access—memory locations having one transistor, or what are known as single-transistor memory locations, are usually used. Besides the transistor, which forms a read transistor, this type of single-transistor memory location includes a storage capacitor. An item of information is stored in the storage capacitor in the form of an electrical charge that represents a logical quantity of 0 or 1. By actuating the read transistor via a word line, this information can be read out via a bit line.
Because storage density is increasing from one generation of memory to the next, the required surface area of the memory location must be reduced from generation to generation. Because the reduction of the size of the memory location is limited by the minimum structural size that can be produced in the respective technology, this is also associated with a modification of the structure of the memory locations. Thus, up to the 1 MBit generation of DRAM cell configurations, both the read transistor and the storage capacitor were realized as planar components. Beginning with the 4 MBit memory generation, it has been necessary to configure the storage capacitor and the read transistor three-dimensionally.
Herein, the storage capacitors are not realized planar, but rather in trenches. These types of memory locations are known as deep trench memory locations.
This type of storage capacitor typically consists of two electrodes which are divided by a dielectric and which are disposed adjacent one another in a trench and surrounded by a common insulator layer. The trenches are installed in a semiconductor substrate and terminate at the surface thereof. The semiconductor substrate is usually formed by a silicon wafer. The read transistor includes a gate electrode and a source/drain region. The gate electrode is installed on the top surface of the semiconductor substrate at a defined remove from the storage capacitor; the source/drain region is generated by implanting dopants.
In known DRAM cell configurations, the trenches for the storage capacitors are typically installed in a multistep process including the following steps:
First, a mask layer, which is typically formed by an SiO
2
layer, is applied on the wafer that forms the semiconductor substrate. A photosensitive resist mask consisting of a resist layer and an underlying antireflective layer is applied over this mask layer. To generate the resist mask, a hole pattern that corresponds to the structure of the trenches is installed in the resist layer using known photolithography processes.
Recesses are then etched into the mask layer through the holes of the resist mask. A hard mask is created from the mask layer by this etching process, which is known as DTMO etching. This hard mask is in turn used for a second etching process, what is known as DT etching, in which the trenches are etched into the semiconductor substrate through the recesses of the hard mask.
Due to the rapid advancement of technology in the field of DRAM memory locations, equally high capacities are required for deep trench memory locations of this type, given smaller and smaller dimensions. To satisfy this requirement, it is necessary that the trenches of the memory locations have optimally large depths. This in turn necessitates optimally long etch times in the DT etching process. To satisfy this requirement, the layer thickness of the SiO
2
layer that forms the hard mask must be optimally large. However, the layer thickness of the hard mask is limited by the construction of the resist mask, particularly its layer thickness. With the contemporary known methods of lithography, resist masks can only be structured up to limited layer thicknesses. For this reason, the layer thicknesses of hard masks that can be used in known DRAM cell configurations are limited to a maximum of approximately 850 nm. The depths of the trenches that can be obtained, and thus the memory location capacities that can be achieved therewith, are undesirably low.
Another problem is that a damaging of the wafer edge in the subsequent etching of the trenches results in the emergence of what is known as black silicon at the edge of the wafer. This is a matter of a local buildup of raw needle-shaped silicon structures in the region of the wafer edge. The wafer is unfit for production in this region due to the high density of defects, so that DRAM cell configurations situated in this region or near it are rejected, thereby undesirably lowering the yield in the manufacturing of DRAM cell configurations.
In response to this problem, the edge of the wafer is typically covered with a collar during the DT etching and/or the DTMO etching. Such a collar is a matter of an etch-resistant ring that is placed over the wafer tightly and that acts as a diaphragm during the execution of the etching processes.
The use of the collar substantially prevents the formation of black silicon. However, the disadvantage of this method is that the collar influences the etching process such that slanted etching profiles instead of vertical profiles are obtained in the environment of the collar in the etching process. This is true particularly of the DTMO etching process for producing the hard mask.
This creates an undesirable shifting of the trenches to the active regions of the DRAM cell configuration, which can ultimately impair the functioning of the overall DRAM cell configuration.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for producing trenches used in forming storage capacitors of DRAM cell configurations which overcomes the above-mentioned disadvantageous of the prior art methods of this general type, and in which the produced memory locations of the DRAM cell configurations have an optimally high capacity with a simultaneously high quality.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method that includes the following steps: First, a first and a second mask layer are applied on a wafer that forms a semiconductor substrate. The first mask layer is considerably thinner than the second, underlying layer. A resist mask is then applied on the first mask layer. This is followed by structuring recesses in the first mask layer in correspondence with the hole pattern of the resist mask by a first etching procedure, whereby the first mask layer can be etched selectively with respect to the resist mask. Lastly, recesses are structured in the second mask layer through the recesses of the first mask layer by a second etching process, whereby the second mask layer can be etched selectively with respect to the first mask layer.
The basic idea of the present invention thus consists in providing a two-stage hard mask for producing the trenches.
Herein, the thickness of the first mask layer, which forms the upper level of the hard mask, is considerably thinner than the second mask layer, which forms the lower level of the hard mask. This structure is inventively achieved in that a material that can be etched selectively with respect to the resist mask is selected for the first mask layer, and a material that can be etched selectively with respect to the first mask layer is used for the second mask layer. The first mask layer preferably consists of polysilicon or crystalline silicon, whereas the second mask layer consists of an oxide, preferably SiO
2
.
When it is constructed this way, the first mask layer can be easily structured using the resist mask, and the relatively small layer thickness of the resist mask suffices for the structuring. The layer thickness of the first mask layer is preferably less than 250 nm and can be reduced to a layer thickness of approximately 100 nm. The layer thickness of the second mask can reach values of 850 nm and above because of the selectivity o
Brencher Lothar
Rudolph Uwe
Stegememann Maik
Greenberg Laurence A.
Ho Hoai
Infineon - Technologies AG
Locher Ralph E.
Stemer Werner H.
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