Method for producing thin substrate layers

Details Method for producing thin substrate layers Method for producing thin substrate layers

2001-03-22

2002-07-09

Fahmy, Wael (Department: 2823)

Semiconductor device manufacturing: process

Bonding of plural semiconductor substrates

Thinning of semiconductor substrate

C438S406000, C438S456000, C438S967000, C257S347000

Reexamination Certificate

active

06417075

ABSTRACT:

FIELD OF APPLICATION
The present invention relates to a method of producing thin substrate layers, specifically thin semiconductor zones possibly containing integrated circuits.
It may be expedient for many present and future applications of electronic components and integrated circuits (ICs) in particular to restrict the overall thickness of these ICs or the semiconductor zones with the ICs to a few micrometers. Such thin circuits present a very low mass and have a very small overall height. They are mechanically flexible, adapt themselves to the thermo-mechanical behaviour of a substrate and reduce problems in disposal on account of their small volume. All these advantages may gain even more importance within the general framework of future disposable electronics. As early as to date thin electronic devices and circuits for fields of application such as flat panel displays, where ICs are bonded to glass, mechatronics, where the ICs are bonded to metal, and high-power electronics (transistors, thyristors, diodes with vertical conduction) are of great interest.
In silicon technology, integrated circuits are manufactured on substrates, the so-called wafers. These wafers consist of mono-crystalline silicon which present, in typical cases, a thickness of 700 &mgr;m and a diameter of 200 mm at present and of 300 mm in the near future. The definition of the thickness of the substrates to 700 &mgr;m offers several aspects in terms of manufacturing technology and also physics. For instance, the precision and the yield in slicing or sawing of the crystal rods drawn from the melt and their subsequent polishing, on the one hand, are important, on the other hand the mechanical stability and a sufficient thermal mass must be ensured during the actual processing of the ICs.
After the production of the integrated circuits or devices in terms of semiconductor technology the wafers and hence the individual chips of the wafer must be thinned to a residual thickness as small as 200 &mgr;m and even down to 120 &mgr;m at present in order to be suitable for integration into housings or on pc boards in particular.
Processing of the devices or circuits on cantilever wafers which are already thinned is normally ruled out because the mechanical stability, the thermal load-bearing capacity et. is by no means sufficient to this end below a thickness of 50 &mgr;m. Moreover, the process development and the entire manufacturing equipment are designed and set for wafers of conventional thickness.
The thinning of the completely processed wafer Is normally realised by polishing. In this process the rear side of the wafer is mechanically removed by means of a polishing paste and suitable abrasive-carrying agents up to the desired residual thickness. Being a monocrystalline substance, silicon cannot be subjected to chipping operations. In the course of polishing rather so-called micro-fissures occur, which are due to the crystalline nature and which may propagate up to the device region of the wafer and destroy the functional operability of the circuits if the process is inappropriately managed. As a consequence of this situation the residual thickness of the silicon substrates, that can be achieved by polishing, is restricted, as a rule to a thickness corresponding to 5 to 10 times the size of the abrasive grains.
One possibility to solve this problem consists in the use of very fine abrasive grains up to diameters of a few hundreds of nanometers, This entails, however, a dramatic reduction of the removal rate so that the thinning process requires a very long time.
For a reduction of the residual thickness below the values occurring in the conventional grinding process it is necessary, as a rule, to employ particularly gentle polishing methods. An appropriate process which attempts to combine the advantages of grinding, wet-chemical etching and so-called CMP (chemical mechanical polishing) is published, for instance, in the paper by D. Bollmann et al., Abstract No. 2115, Proceedings, The Electrochemical Society Meeting, Paris 1997. As an alternative, wet and also dry etching methods have been tried. The latter processes, however, lead to a high thermal load on the substrate and the devices applied thereon, with the necessary amount of the removal rate.
On principle, these methods involve the thinning of the wafer after processing of the circuits. The processes leading to thinning are thus performed on a wafer on the surface of which the entire high added value in chip production is already accumulated. Faulty thinning correspondingly leads to a reduction of the yield and hence in high losses in value. Moreover, the observation of the desired residual thickness is rendered rather difficult on account of the reduced possibility of (local) measurement of the residual thickness, which is impaired by the implemented devices.
A fundamental way out of the problems Involved in thinning of wafers presenting a high accumulated added value and in the complex thickness measurement consists in the application of so-called SOI wafers. SOI wafers carry an insulating layer buried just below the surface, as a rule in the form of an SiO
2
layer. There are several methods available for the production of such SOI wafers (cf., for instance, W. P. Maszara et al.: “SOI Materials for Mainstream CMOS Technology”, in: SOI Technology and Devices VII, ed.: S. Christoloveanu, The Electrochemical Society Proceedings 97-23, 1997) which will be outlined in the following.
In SOS (silicon on sapphire) techniques an epitactical silicon layer is deposited on a polished Al
2
O
3
crystal. This approach is successful as a result of the approximately equal lattice constant of both materials. However, crystalline Al
2
O
3
wafers must be used, which renders this method very expensive and is applicable only in the case of extremely high-price applications.
In ZMR (zone melting recrystallization) technique poly-silicon is deposited on a wafer covered with SiO
2
and then crystallised by a local fusing and solidifying process. The crystal quality, the crystallite size, etc. of these wafers does, as a matter of fact, no longer satisfy the demands current in today's CMOS technology.
In the SIMOX (Separation of implanted oxygen) technique a high-dose ion implantation just below the surface of the silicon wafer creates a stoichiometric SiO2 layer which, in the case of an appropriate process management, i.e. thorough healing of the crystal damage caused by implantation, leaves the extremely thin silicon layer monocrystalline that is located thereabove and will carry devices later on.
In the BESOI (bonded etched-back silicon on insulator) technique two oxidized silicon wafers are fixedly fastened on each other by thermal bonding and covalent bonds so established. Then one of the two wafers is thinned back to the useful thickness. A specific variant of the BESOI technology (“SmartCut® OR IonCut) uses special methods of thinning which are based on the implementation of a layer created by means of ion implantation and buried below the surface, along which layer the useful layer is split off that is bonded onto the second wafer (manipulating) wafer. This may be achieved by forming gas bubbles by means of hydrogen or helium implantation (cf. European Patent EP-A 0 533 551 or M. Bruel et al. in_“Unibond SOI Wafers Achieved by Smart-Cut® Process” in: SoI Technology and Devices VIII, ed.: S. Christoloveanu, The Electromechanical Society Proceedings 97-23, 1997) or by detaching a fusing intermediate layer (cf. German Patent DE 1{circumflex over ( )}95 46 179 A1). In both cases the production of a BESOI wafer is successful without repeated grinding or etching of major parts of a monocrystalline wafer laboriously produced before.
SOI wafers produced according to the SIMOX and BESOI processes have been developed up to a stage ready for application in the past few years. They are applied in the fields of application high-temperature electronics and “low power electronics” to an ever-increasing extent and are commercially available in high numbers of units.
Such SO

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