Metal fusion bonding – Process – With protecting of work or filler or applying flux
Reexamination Certificate
2002-01-17
2004-03-02
Edmondson, Lynne (Department: 1725)
Metal fusion bonding
Process
With protecting of work or filler or applying flux
C228S225000, C228S033000, C228S039000, C216S018000, C029S840000
Reexamination Certificate
active
06698648
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a process for the production of at least one solderable surface in selected solder regions and of at least one functional surface in function regions differing from the solder regions on circuit carriers provided with copper surfaces as well as of corresponding circuit carriers.
2. Brief Description of the Related Art
Circuit carriers serve to receive active and passive components. In principle, a distinction is made between conventional printed circuit boards and chip carriers. Whereas the first ones are packed with passive components such as capacitors and resistors for example and with cased semiconductor components, the chip carriers serve for the assembly of uncased semiconductor components. In parts, several uncased, and possibly cased semiconductor components too, are integrated into a single chip carrier. Such hybrid circuits are referred to as multichip modules. For some time, uncased semiconductor components have been directly integrated, without prior assembly, into a circuit carrier together with passive components. Such circuit carriers are so-called COB-(Chip-On-Board)-printed circuit boards.
Various processes for producing circuit carriers intended to be packed with passive components and uncased semiconductor components have been known. First, the circuit pattern that is needed for this purpose and that is made from copper is formed by means of well-known processes. Then, layers of gold for example are deposited to allow the circuit carriers to be packed. On one side, these layers serve to form solderable surfaces which are necessary for the insertion of passive components. On the other side, the gold surfaces are also suited for bonding cased and uncased semiconductor components.
U.S. Pat. No. 5,364,460 for example indicates that, among others, layers of gold are deposited by means of electroless plating onto printed circuit boards and cards for integrated circuits.
Coating copper structures on printed circuit board material is indicated in DE 43 11 266 A1. There, in one embodiment, parts of the printed circuit board's surface are first plated with gold, palladium, indium, rhodium, nickel, tin, lead or alloys of these elements, preferably with palladium, in those regions that are not to be provided with a solderable surface. Prior to this, the surface areas that are to be provided with the solderable surface are provided with a covering mask. Then, the mask is removed again. Thereupon, a solderable metal surface of a Tin/lead alloy is formed by means of electroless plating.
DE 33 12 725 A1 describes a method of producing thin film strip conductors with through hole connections that can be bonded and soldered on electrically non-conductive carriers in which the areas that can be bonded and soldered are formed by galvanic deposition of a layer of gold or of nickel/gold, respectively.
Gold layers are also formed to produce electrical contacts that may be opened, such as plug contacts for plugging the packed circuit carriers in contact plugs, and areas of contact for producing press buttons. DE-OS 1 690 338 mentions a method of producing multiple plug-type connections with gold surfaces in which, in the region of the plug-type connections and on the other circuit lines, a tin/lead alloy is first deposited by electroplating on a printed circuit board material that has been completely plated with a layer of copper whereupon nickel and gold are deposited in the region of the plugs onto the layer of terne metal, the bare layer of copper being etched upon removal of the electroplating lacquer. The reference indicates that the relatively soft layer located underneath the layer of nickel/gold is disturbing and that it has been observed that the circuit lines happen to be etched through at the transition zone between the gold contacts and the tin/lead alloy.
DE 197 45 602 C1 further indicates that layers of gold are utilized for producing surfaces that are capable of being soldered, glued or bonded. The methods described in this reference permit to produce circuit carriers of the finest structure with surface-mounted semiconductor circuits in which the circuits are connected to mating connecting pads on the circuit carrier by way of Ball-wedge-Bonds.
Layers of gold that have been produced by means of electroplating are not applied directly onto the copper surfaces. According to U.S. Pat. No. 5,364,460 for example, a layer containing nickel is deposited first and then the film of gold is deposited onto the layer containing nickel. The nickel containing layer is preferably formed by a layer of Ni/B or Ni/P which is deposited by means of electroless plating U.S. Pat. No. 5,470,381 also teaches to first deposit a layer containing nickel and then a layer of gold.
DE 197 45 602 C1. U.S. Pat. Nos. 5,202,151, 5,318,621, 5,364,460 and 5,470,381 describe methods of electroless gold plating.
Instead of the layer containing nickel, layers of another metal, of cobalt or palladium for example, can be deposited onto the copper surfaces prior to forming the layer of gold. In this respect, U.S. Pat. No. 5,202,151 proposes among other suggestions to apply a layer of cobalt to the copper surfaces and to deposit the layer of gold subsequently. Instead of electroplating a layer of nickel or cobalt, a layer of nickel or cobalt can also be applied by means of a vapor deposition process or by sputtering and then be electrolessly gold plated. DE 197 45 01 C1 moreover indicates a method of producing gold layers on a work piece that is provided with a palladium surface.
Instead of using a layer of gold, layers of palladium can also be utilized. DE 42 01 129 A1 describes a method of producing a wiring board in which a film of palladium is formed on the copper parts of the board by means of electroless plating, the palladium surfaces being produced on double-faced wiring boards in order to bond components of the surface-mounted technology-type by soldering them. Furthermore, U.S. Pat. No. 4,424,241 indicates a process of electrolessly plating palladium in which the layers of palladium formed serve for pattern delineation in electric circuits such as integrated circuits.
To produce layers of gold on the entire surface of the circuit carrier proved to be too expensive.
In most cases, smaller bondable areas only are needed on the surfaces of the circuit carriers while other surface areas only need to be suited for receiving components that are mounted by soldering. It has moreover been noticed that layers of gold with underlying layers of nickel for soldering so-called Ball-Grid-Arrays (BGA) lead to brittle fractures when the packed circuit carrier is subject to mechanical and/or thermal stress.
For this reason, a process has been developed in which those areas onto which components are intended to be soldered are first covered with an appropriate mask, e.g. a photoresist that can be structured, whereupon a layer combination of nickel and gold is deposited on the still bare areas. Then, the mask is cleared off the surface of the circuit carrier. Subsequently, an organic protective coating is formed by means of an aqueous acid solution of alkyl imidazole or of alkyl benzimidazole compounds. This protective coating prevents the copper surfaces from oxidizing and preserves solderability of the copper surfaces.
First, with this process, the combination layer of nickel and gold is only formed in those areas in which components are bonded or in which electric contact areas are needed. Second, this process eliminates the problem associated with soldering by means of the BGA technique.
It has been observed in carrying out this process though, that the appearance of the gold surfaces unfavorably changes in that the layers change to a reddish color. Additionally, the layer of nickel underneath the layer of gold is damaged by the processing chemicals. As a result, the electrical contact resistance is increased so that the possibility of using the combination layer of nickel and gold to form electrical contact areas is limited.
Sol
Backus Petra
Mahlkow Hartmut
Wunderlich Christian
Atotech Deutschland GmbH
Bonini, Jr. Frank J.
Earley III John F. A.
Edmondson Lynne
Harding Earley Follmer & Frailey
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