Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates – Subsequent separation into plural bodies
Reexamination Certificate
2000-12-04
2002-07-16
Ghyka, Alexander G. (Department: 2812)
Semiconductor device manufacturing: process
Bonding of plural semiconductor substrates
Subsequent separation into plural bodies
C438S455000, C438S459000
Reexamination Certificate
active
06420243
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to semiconductor manufacturing, and, more particularly, to a method for producing and wafers by delamination.
BACKGROUND OF THE INVENTION
A general introduction to the fabrication of SOI wafers by the hydrogen ion delaminating method may be found in Aspar et al., “Basic mechanisms involved in the smart-cut-process”, Microelectronic Engineering, Vol. 3, No. 1 to 4, Jun. 1, 1997, pages 233 to 240.
The continuing volume growth of portable systems with their increasing demand for better performance and autonomy makes SOI (silicon on insulator) a very attractive approach for large-volume integrated circuit production dedicated to low-voltage, low-power, high-speed systems. The capability of SOI circuits to operate at 1 Volt or below even in the case of DRAM's has been demonstrated as a best compromise between speed and power consumption. SOI is also appropriate for the gigabit DRAM generation and the system on ship approach.
FIG. 1
with diagrams
10
-
50
illustrates a known method for producing SOI wafers by hydrogen ion delamination. According to diagram
10
, two silicon mirror-polished wafers
1
,
2
, namely a base wafer
1
to be a base and a bond wafer
2
to become a SOI wafer are prepared according to device specifications.
As shown in diagram
20
, at least one of the wafers
1
,
2
, here the bond wafer
2
, is subjected to thermal oxidation so as to form on the surface thereof an oxide film
3
having a thickness of about 0.1 &mgr;m to 2.0 &mgr;m.
As depicted in diagram
30
, hydrogen ions H
+
are implanted into one surface of the bond wafer
2
on which the oxide film
3
is formed in order to form a fine bubble layer
4
which extends in parallel to the surface at a position corresponding to the mean depths of the ion implantation step. The ion implantation temperature amounts preferably to 25 to 450° C.
Having regard to diagram
40
, the base wafer
1
is superimposed on the hydrogen ion-implanted surface of the hydrogen ion-implanted bond wafer
2
via the oxide film
3
, and both wafers are brought in close contact with each other. When the surfaces of the two wafers are brought into contact with each other at ambient temperature in a clean atmosphere, the wafers adhere to each other without use of adhesive or the like, which is called direct bonding phenomena.
As illustrated in diagram
50
, then a heat treatment is performed for delaminating (splitting) such that a delamination wafer
5
is delaminated from a SOI wafer
6
which is composed of the SOI layer
7
, a buried oxide layer
3
and the base wafer
1
. In this process step, the fine bubble layer
4
formed by the ion implantation step is used as a delamination plane. The heat treatment is performed, for example, at a temperature of about 500° C. or higher in an inert gas atmosphere so as to cause crystal rearrangement and bubble cohesion such that the delaminated wafer
5
is delaminated from the SOI wafer
6
.
Further process steps which are not illustrated in
FIG. 1
may comprise the steps of annealing up to temperatures of the order of 1100° C. in order to strengthen the bonds and chemical-mechanical polishing in order to provide a smooth surface. Preferably, the bonding heat treatment is performed in an inert gas atmosphere for 30 minutes to 2 hours.
In another known approach, a heat treatment in a reducing atmosphere containing hydrogen may be performed in order to remove the damage layer on the surface of the SOI layer and improve the surface roughness.
Finally, if the delaminated wafer
5
has an appropriate thickness, it can be used as a new bond wafer or base wafer after an appropriate treatment. A major disadvantage of the known technique is that it is not very economical.
The present invention seeks to provide to a method for producing SOI wafers by delamination which mitigates or avoids these and other disadvantages and limitations of the prior art and provides a more economical solution.
REFERENCES:
patent: 5714395 (1998-02-01), Bruel
patent: 5882987 (1999-03-01), Srikrishnan
patent: 5920764 (1999-07-01), Hanson et al.
patent: 5966620 (1999-10-01), Sakaguchi et al.
patent: 6124185 (2000-09-01), Doyle
patent: 6245645 (2001-06-01), Mitani et al.
patent: 6284629 (2001-09-01), Yokokawa et al.
patent: 6312797 (2001-11-01), Yokokawa
“Basic mechanisms involved in the Smart-Cut-process”, Microelectronic Engineering, vol. 3, No. 1 to 4, Jun. 1, 1997, pp. 233 to 240.
Advertisement papers by Soitec SA, 38 190 Bernin, France.
Stanley Peter
Stanley Timothy Daryl
Ghyka Alexander G.
Motorola Inc.
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