Active solid-state devices (e.g. – transistors – solid-state diode – Bipolar transistor structure – With specified electrode means
Reexamination Certificate
2002-03-26
2003-11-04
Quach, T. N. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Bipolar transistor structure
With specified electrode means
C257S754000, C438S330000, C438S364000, C438S655000
Reexamination Certificate
active
06642606
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention is directed to a method for producing siliconized polysilicon contacts in integrated semiconductor structures, to the employment of the method for manufacturing a transistor, as well as to a transistor that can be obtained according to the inventive method.
In the manufacture of integrated semiconductor structures, the problem frequently arises that the resistance of polysilicon structures employed as interconnects must be selectively lowered. At the same time, the resistance of other polysilicon structures located in the integrated semiconductor, which is to be manufactured, should remain high since these, for example, are to be employed as resistors within the integrated circuit. In order to reduce the resistance of a polysilicon structure, the structure is often provided with a silicide layer. However, the manufacturing problem of siliconizing only specific polysilicon structures but not siliconizing others, for example those that are to be employed for resistors will occur.
The problem of selective siliconization and solutions known from the prior art shall be discussed below on the basis of a specific example of the employment in an integrated transistor. It is self-evident, however, that the inventive method can also be applied to other fields of employment in semiconductor production and is not intended to be limited to the employment in the manufacture of integrated transistors.
FIG. 1
shows a bipolar transistor in an integrated semiconductor known in the prior art. The actual, active transistor
1
is thereby composed of three juxtaposed, differently doped regions of semiconductors, the emitter region
2
, the base region
3
as well as the collector region
4
. Dependent on the doping, a distinction is made between pnp-transistors, and npn-transistors, whereby the sequence of the letters identifies the sequence of the doping in the emitter, base and collector region.
Over and above this, a transistor arranged in an integrated circuit also has further auxiliary structures surrounding it, and these structures serve, on the one hand, for isolating potentials and, on the other hand, for the elimination of the currents from the active transistor region
1
. The emitter region
2
is connected via an emitter contact
5
, which is usually composed of polysilicon, to an emitter interconnect
6
of, for example, aluminum. The base region
3
is connected via a base contact
7
to a base interconnect
8
. The collector region
4
, finally, is connected via what is referred to as a buried layer
9
, which is located under the other structures, and an intermediate layer
10
as well as a collector contact
11
to a collector interconnect
12
. Various silicon oxide insulating layers
13
as well as spacer insulators
14
serve the purpose of the electrical separation of the various, electrically conductive structures.
What is referred to as the extrinsic base resistance, which is the resistance between the base
3
and the base interconnect
8
, is, in addition to the transit frequency and the base-collector capacitance, the critical transistor parameter in bipolar transistors that defines important characteristic quantities of the transistor such as its maximum oscillation frequency, its gain, its minimum noise after, its gate delay times etc. Thus, valid here, for example, are
f
max
≈
f
T
8
π
·
R
B
·
C
BC
(
1
)
whereby
f
max
: maximum oscillation frequency
f
T
: transit frequency
R
B
: base resistance
C
BC
: base-collector capacitance
or
F
min
≈
1
+
1
β
+
f
f
T
2
·
I
C
V
T
R
B
(
1
+
f
T
2
β
·
f
2
)
+
f
T
2
β
·
f
2
whereby
F
min
: minimum noise factor
&bgr;: gain
f: frequency
f
T
: transit frequency
I
C
: collector current
V
T
: thermal voltage
R
B
: base resistor apply.
In self-aligned silicon bipolar transistors, the base resistance is essentially composed of three parts, these being referred to below as R
B,l
, R
B,e
and R
B,T
. The inner part R
B,l
occurs due to the resistance of the base zone in the active transistor
1
under the emitter region
2
. The external part R
B,e
describes the resistance of the polysilicon track
7
that forms the base content. R
B,T
represents the base resistance that occurs due to a lightly doped zone under the self-aligned emitter base insulation of the spacer insulator
14
at the active transistor. This region is generally referred to as link region in the literature.
Optimizations can be undertaken at all three regions in order to reduce the base resistance. For typical applications, for example, in micro-transistors or ultra high frequency circuits, the transistor is configured in an arrangement with two base contacts instead of one base contact
7
(not shown).
The second base contact can, for example, be arranged between the emitter contact and the collector contact. The reduction of the base resistance that is thus achieved, however, is purchased at the expense of an increased space requirement, higher capacitances, a higher power consumption and lower transit frequency.
The advantages of the low base resistance of a transistor having two base contacts and the small structure of a transistor having one base contact can be united when the polysilicon that serves the purpose of base contacting is siliconized, i.e. provided with a silicide layer. The significantly lower film contact of the silicide compared to the polysilicon leads to the fact that the transistor side facing away from the base contact is also connected low-impedance to the base contact via the silicide and, thus, a similar, low base resistance as given a transistor with two base contacts results. Moreover, the resistance inherent in the base contact is reduced.
In addition to being employed for the above-described function, silicide layers can also be utilized as additional wiring level. This enables the optimization of the wiring layout and, thus, of the circuit performance capability.
In a simple, previously known method for siliconization, the siliconization step is introduced immediately after the coating and structuring of the polysilicon. This method, however, has the serious disadvantage of siliconizing not only the desired base terminal regions as well as, potentially, additional interconnects but of siliconizing all uncovered polysilicon regions, i.e. even those wherein a siliconization is unwanted. However, it is precisely the silicon layers that are employed for the base contact as well as the emitter and collector terminal in integrated circuits that are also employed for realizing ohmic load resistors in the circuits. Due to the complete siliconization, the film resistance of the polysilicon layer or layers become so low that resistors (that typically exhibit values from 50 through 1000 ohms) can no longer be meaningfully produced with the assistance of these layers. When a silicide is therefore to be integrated into an integrated circuit, methods are thus necessary that prevent a siliconization in the region of the load resistors. Such methods are referred to in the literature as “silicide blocking”. A known method for silicide blocking is implemented with the assistance of photolithography. With the assistance of a resist mask, the dielectric that surrounds the resistor and transistor regions is covered in those regions wherein no silicide formation should occur. With an etching, the dielectric is opened in regions to be siliconized, i.e. removed, and a siliconization is subsequently implemented. The introduction of this additional photolithographic step means a clear increase in the process complexity compared to methods that do not employ a siliconization and thus leads to considerably increased process costs that often make the use of a silicide seem not meaningful despite the improvement of the transistor performance capability.
SUMMARY OF THE INVENTION
The present invention is therefore based on the object of offering a method wherein a selective, i.e. designational siliconization of pol
Infineon Technologies Aktiengesellschaft
Quach T. N.
Schiff & Hardin & Waite
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