Method for producing self-aligned LDD CMOS, DMOS with deeper sou

Details Method for producing self-aligned LDD CMOS, DMOS with deeper sou Method for producing self-aligned LDD CMOS, DMOS with deeper sou

1993-06-02

1994-08-23

Thomas, Tom

Fishing, trapping, and vermin destroying

437 41, 437 57, H01L 21265, H01L 2170

Patent

active

053407563

ABSTRACT:
A low-concentration region is formed by ion implanting a P-well with P.sup.+ using a gate as a mask, then an N-well is ion-implanted with As.sup.+ and B.sup.+ using a resist film and the gate as a mask to form a DMOSFET having a double-diffused drain structure. Then, the gate and an insulation material are used as a mask to ion-implant the P-well with As.sup.+ to form a CMOSFET having a lightly doped drain structure. After that, the N-well is ion-implanted with BF.sub.2.sup.+ through an opening to connect a P base region with a P base-contact region. The source/drain and p-base regions of the DMOS device are formed deeper than those of the CMOS device. Incorporation of a bipolar transistor is also disclosed. All devices are formed on the same substrate.

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