Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2006-03-14
2006-03-14
Schillinger, Laura M. (Department: 2813)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S125000, C438S127000
Reexamination Certificate
active
07011985
ABSTRACT:
A method for producing miniature amplifier and signal processing unit includes the steps of:producing arrays of individual integrated circuits on a side of a wafer, where each circuit has a number of I/O connection points;providing a number of solder connection pads at each integrated circuit for redistribution of the I/O connection points of the integrated circuit;coating the side of the wafer having the solder connection pads with a protection coating and ensuing through going apertures in the coating to provide electrical contact with the solder connection pads;applying electrical components onto the coating and gaining electrical contact with the solder connection pads through the apertures of the coating material; andsingulating the individual amplifiers from the wafer and ensuring light protection of the edges and possible unprotected side of the amplifiers.
REFERENCES:
patent: 6338980 (2002-01-01), Satoh
patent: 6787398 (2004-09-01), Tateoka et al.
patent: 6916719 (2005-07-01), Knight et al.
patent: 2004/0235218 (2004-11-01), Skindhoj et al.
patent: WO 2103784 (2002-12-01), None
Patent Abstracts of Japan, of JP 2001-127206, published May 11, 2001, entitled “Manufacturing Method of Chip-Scale Package and Manufacturing Method of IC Chip” to Sato Tetsuo (Citizen Watch Co., Ltd.).
Petersen Anders Erik
Skindhøj Jørgen
Gossett PLLC Dykema
Oticon A/S
Schillinger Laura M.
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