Method for producing interlevel stud vias

Details Method for producing interlevel stud vias Method for producing interlevel stud vias

1992-02-20

1993-10-12

Maples, John S.

Fishing, trapping, and vermin destroying

437238, 437978, 437979, H01L 21441

Patent

active

052525163

ABSTRACT:
Metallized level is covered with a relatively thick non-conformal oxide layer, such as sputtered quartz (SiO.sub.2). This layer is, in turn, covered with a relatively thin oxide blanket resistant to RIE, such as aluminum oxide (Al.sub.2 O.sub.3) or Yttrium Oxide (Y.sub.2 O.sub.3). A mask, with exposed via opening, is formed in a conventional manner on the aluminum oxide surface and the aluminum oxide in the open areas is removed, for example Al.sub.2 O.sub.3 is etched with BCl.sub.3 and O.sub.2 gases or wet etch with H.sub.3 PO.sub.4. An RIE process is used to form vias.

REFERENCES:
patent: 4686000 (1987-08-01), Heath
patent: 4721689 (1988-01-01), Chaloux et al.
patent: 4767724 (1988-08-01), Kim et al.
patent: 4789648 (1988-12-01), Chow et al.
patent: 4933303 (1990-06-01), Mo
patent: 4936950 (1990-06-01), Doan et al.
patent: 4997789 (1991-03-01), Keller et al.

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