Method for producing integrated microsystems

Details Method for producing integrated microsystems Method for producing integrated microsystems

2005-11-01

2005-11-01

Le, Thao P. (Department: 2818)

Semiconductor device manufacturing: process

Chemical etching

Liquid phase etching

C438S745000, C438S689000

Reexamination Certificate

active

06960536

ABSTRACT:
A method for producing a microsystem that has, situated on a substrate, a first functional layer that includes a conductive area and a sublayer. Situated on the first functional layer is a second mechanical functional layer, which is first initially applied onto a sacrificial layer situated and structured on the first functional layer. In addition, a layer is situated on the side of the sublayer facing away from the conductive area. The layer constitutes a protective layer on the first functional layer that acts in areas during a sacrificial layer etching process so that during removal of the sacrificial layer no etching of the areas of the first functional layer covered by the protective layer occurs, and that in the region of the areas of the first functional layer implemented without the protective layer the sublayer is removed essentially selectively to the conductive area at the same time as the sacrificial layer. Further, a method is described for producing integrated microsystems having silicon-germanium functional layers, sacrificial layers containing germanium, and open metal surfaces. The sacrificial layers containing germanium are at least partially removed in an etching solution, a pH value of the etching solution being kept at least approximately neutral during the etching procedure using a buffer.

REFERENCES:
patent: 6210988 (2001-04-01), Howe et al.
patent: 6261964 (2001-07-01), Wu et al.
patent: 38 74 411 (1992-10-01), None
patent: 0 292 057 (1988-11-01), None
Franke et al., “Post-CMOS Mudular Integration Of Poly-SiGe Microstructures Uing Poly-Ge Sacrificial Layers”, Solid-State Sensor and Actualor Workshop, Hilton Head, SC Jun. 2000, pp. 18-21.
Franke et al., “Post-CMOS Modular Integration of Poly-SiGe Microstructures Using Poly-Ge Sacraficial Layers”, Solid-State Sensor and Actuator Workshop, Hilton Head, SC, Jun. 2000, pp. 18-21.

Affiliated with

Also associated with

Rating

Method for producing integrated microsystems does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for producing integrated microsystems, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for producing integrated microsystems will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3481449