Stock material or miscellaneous articles – Composite – Of silicon containing
Reexamination Certificate
1998-12-11
2001-12-11
Lam, Cathy (Department: 1775)
Stock material or miscellaneous articles
Composite
Of silicon containing
C428S448000, C428S469000, C428S641000, C428S642000
Reexamination Certificate
active
06329063
ABSTRACT:
FIELD OF THE INVENTION
The invention pertains to the field of heteroepitaxial growth of single crystal thin layers on substrates of different lattice constants. More particularly, the invention pertains to forming stress-engineered substrates as platforms for the growth of high quality heteroepitaxial layers.
BACKGROUND OF THE INVENTION
Heteroepitaxy refers to growth of single crystal thin layers on substrates of different lattice constants (or atomic spacing). If achievable, high quality semiconductor heteroepitaxial layers have many important applications in electronics and optoelectronics. Their benefits include enhanced speed and power efficiency for RF amplifiers in wireless communication, and enhanced quantum efficiency and operating wavelength range for optoelectronic devices such as lasers, LEDs, and detectors. However, in reality, with exceptions of very few cases, the great potential benefits of heteroepitaxial films can not be realized because the heteroepitaxial layers achievable today contain a large number of defects, specifically threading dislocations. These dislocations in the heteroepitaxial layers degrade device performance and reliability so much that heteroepitaxy is rarely used for any commercial applications. Therefore, to realize the great potential of heteroepitaxy, it is imperative to find ways to significantly reduce the number of threading dislocations in the heteroepitaxial layers.
U.S. Pat. No. 5,294,808 (Lo) requires ultra thin substrates or a sacrificial substrate for dislocation gettering. U.S. Pat. No. 5,091,133 (Fan et al.) uses thermal stress from thermal annealing/cycling by interrupting the growth. The stress produced in the method of the '133 patent only exists during thermal annealing. U.S. Pat. No. 5,659,187 (Legoues et al.) discloses a method wherein the dislocation bending force is only over the strain graded buffer layers. Furthermore, new dislocations may be nucleated in the strain graded buffer layers as they bend the existing dislocations.
Referring to
FIG. 1
, when a heteroepitaxial thin film
5
is grown on a substrate
8
, its lattice is initially deformed elastically to match that of the substrate. Hence the stress in the heteroepitaxial material builds up as the film
5
grows thicker. At a certain film thickness, namely the critical thickness, the strain energy is too high to be accommodated by elastic deformation and the thin film becomes plastically deformed by forming dislocations. According to the well established theory, dislocations are most likely nucleated at the surface
7
of the heteroepitaxial layer and then propagate towards the film-substrate interface
6
to become misfit dislocations for strain release. The strain releasing misfit dislocations may be extended over a finite distance until they either reach the edge of the wafer or most likely thread up to the surface
7
of the heteroepitaxial layer.
The formation of the above described “dislocation half loop”, shown at
30
, consists of a section of misfit dislocation
10
and two threading dislocations
20
,
21
. The misfit dislocation
10
portion of the dislocation half loop
30
relaxes the strain and does no harm to devices built in the heteroepitaxial layers since it is confined at the interface. However, the threading dislocation portions
20
,
21
of the half loop
30
run across the entire thickness of the film, thus being detrimental to devices. Therefore, the key to improving the quality of heteroepitaxial film is to minimize the density of threading dislocations while keeping the misfit dislocations for strain release.
SUMMARY OF THE INVENTION
Briefly stated, a method for producing a stress-engineered substrate includes selecting first and second materials for forming the substrate. An epitaxial material for forming a heteroepitaxial layer is then selected. If the lattice constant of the heteroepitaxial layer (a
epi
) is greater than that (a
sub
) of the immediate substrate layer the epitaxial layer is deposited on, then the epitaxial layer is kept under “compressive stress” (negative stress) at all temperatures of concern. On the other hand, if the lattice constant of the heteroepitaxial layer (a
epi
) is less than that (a
sub
) of the immediate substrate layer the epitaxial layer is deposited on, then the epitaxial layer is kept under “tensile stress” (positive stress). The temperatures of concern range from the annealing temperature to the lowest temperature where dislocations are still mobile.
According to an embodiment of the invention, a method for producing a stress-engineered substrate includes steps of:
a) selecting first and second materials for forming the substrate, the first material having a first lattice constant;
b) selecting an epitaxial material for forming a heteroepitaxial layer, the epitaxial material having a second lattice constant;
c) comparing the second lattice constant to the first lattice constant to determine which lattice constant is greater;
d) keeping, when the second lattice constant is greater than the first lattice constant, the heteroepitaxial layer under compressive stress for a range of temperatures, the range of temperatures being from an annealing temperature of the substrate to a lowest temperature where dislocations are still mobile in the heteroepitaxial layer and
e) keeping, when the second lattice constant is less than the first lattice constant, the heteroepitaxial layer under tensile stress for a range of temperatures, the range of temperatures being from an annealing temperature of the substrate to a lowest temperature where dislocations are still mobile in the heteroepitaxial layer.
According to an embodiment of the invention, a stress-engineered substrate for receiving a heteroepitaxial layer thereon includes a first stress control layer having a first lattice constant; a second stress control layer; a joining layer between the first stress control layer and the second stress control layer; a heteroepitaxial layer having a second constant on the first control layer; and means for choosing the first and second lattice constants, such that when the second lattice constant is greater than the first lattice constant, the heteroepitaxial layer is under compressive stress for a range of temperatures, the range of temperatures being from an annealing temperature of the substrate to a lowest temperature where dislocations are still mobile in the heteroepitaxial layer, and when the second lattice constant is less than the first lattice constant, the heteroepitaxial layer is under tensile stress for the range of temperatures.
According to an embodiment of the invention, a stress-engineered substrate for receiving a heteroepitaxial layer thereon includes a first stress control layer; a second stress control layer; a joining layer between the first stress control layer and the second stress control layer; a template layer on the first stress control layer, the template layer having a first lattice constant; a heteroepitaxial layer having a second lattice constant on the template layer; and means for choosing the first and second lattice constants, such that when the second lattice constant is greater than the first lattice constant, the heteroepitaxial layer is under compressive stress for a range of temperatures, the range of temperatures being from an annealing temperature of the substrate to a lowest temperature where dislocations are still mobile in the heteroepitaxial layer, and when the second lattice constant is less than the first lattice constant, the heteroepitaxial layer is under tensile stress for the range of temperatures.
REFERENCES:
patent: 4551394 (1985-11-01), Betsch et al.
patent: 4830984 (1989-05-01), Purdes
patent: 4963949 (1990-10-01), Wanlass et al.
patent: 5011550 (1991-04-01), Konushi et al.
patent: 5091133 (1992-02-01), Kobayashi et al.
patent: 5145793 (1992-09-01), Oohara et al.
patent: 5294808 (1994-03-01), Lo
patent: 5403673 (1995-04-01), Haga et al.
patent: 5444016 (1995-08-01), Abrokwah et al.
patent: 5484664 (1996-01-01), Kitahara et al.
patent: 5659187 (1997-08-01), L
Ejeckam Felix
Lo Yu-Hwa
Fernandez & Associates LLP
Lam Cathy
Nova Crystals, Inc.
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