Semiconductor device manufacturing: process – Making device or circuit emissive of nonelectrical signal – Compound semiconductor
Reexamination Certificate
2002-09-26
2004-12-14
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making device or circuit emissive of nonelectrical signal
Compound semiconductor
C257S103000
Reexamination Certificate
active
06830948
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating Group III nitride compound semiconductors. More particularly, the present invention relates to a method for fabricating Group III nitride compound semiconductors employing epitaxial lateral overgrowth (ELO). The Group III nitride compound semiconductors are generally represented by Al
x
Ga
y
In
1−x−y
N (wherein 0≦x≦1, 0≦y≦1, and 0≦x+y≦1), and examples thereof include binary semiconductors such as AlN, GaN, and InN; ternary semiconductors such as Al
x
Ga
1−x
N, and Ga
x
In
1−x
N (wherein 0<×<1); and quaternary semiconductors such as Al
x
Ga
y
In
1−x−y
N (wherein 0<x<1, 0<y<1, and 0<x+y<1). In the present specification, unless otherwise specified, “Group III nitride compound semiconductors” encompass Group III nitride compound semiconductors which are doped with an impurity so as to assume p-type or n-type conductivity.
2. Description of the Related Art
Group III nitride compound semiconductor are direct-transition semiconductors exhibiting a wide range of emission spectra from UV to red light when used in a device such as a light-emitting device, and have been used in light-emitting devices such as light-emitting diodes (LEDs) and laser diodes (LDs). In addition, due to their broad band gaps, devices employing the aforementioned semiconductors are expected to exhibit reliable operational characteristics at high temperature as compared with those employing semiconductors of other types, and thus application thereof to transistors such as FETs has been energetically studied. Moreover, since Group III nitride compound semiconductors contain no arsenic (As) as a predominant element, application of Group III nitride compound semiconductors to various semiconducting devices has been longed for from the environmental aspect. Generally, these Group III nitride compound semiconductors are formed on a sapphire substrate.
SUMMARY OF THE INVENTION
However, when a Group III nitride compound semiconductor is formed on a sapphire substrate, misfit-induced dislocations occur due to difference between the lattice constant of sapphire and that of the semiconductor, resulting in poor device characteristics. Misfit-induced dislocations are threading dislocations which penetrate semiconductor layers in a longitudinal direction (i.e., in a direction vertical to the surface of the substrate), and Group III nitride compound semiconductors are accompanied by the problem that dislocations in amounts of approximately 10
9
cm
−2
propagate therethrough. The aforementioned dislocations propagate through layers formed from Group III nitride compound semiconductors of different compositions, until they reach the uppermost layer. When such a semiconductor is incorporated in, for example, a light-emitting device, the device poses problems of unsatisfactory device characteristics in terms of threshold current of an LD, service life of an LED or LD, etc. On the other hand, when a Group III nitride compound semiconductor is incorporated in any of other types of semiconductor devices, because electrons are scattered due to defects in the Group III nitride compound semiconductor, the semiconductor device comes to have low mobility. These problems are not solved even when another type of substrate is employed.
The aforementioned dislocations will next be described with reference to a sketch of FIG.
11
.
FIG. 11
shows a substrate
91
, a buffer layer
92
formed thereon, and a Group III nitride compound semiconductor layer
93
further formed thereon. Conventionally, the substrate
91
is formed of sapphire or a similar substance and the buffer layer
92
is formed of aluminum nitride (AlN) or a similar substance. The buffer layer
92
formed of aluminum nitride (AlN) is provided so as to relax misfit between the sapphire substrate
91
and the Group III nitride compound semiconductor layer
93
. However, generation of dislocations is not reduced to zero. Threading dislocations
901
propagate upward (in a vertical direction with respect to the substrate surface) from dislocation initiating points
900
, penetrating the buffer layer
92
and the Group III nitride compound semiconductor layer
93
. When a semiconductor device is fabricated by stacking various types of Group III nitride compound semiconductors of interest on the Group III nitride compound semiconductor layer
93
, threading dislocations further propagate upward, through the semiconductor device, from dislocation arrival points
902
on the surface of the Group III nitride compound semiconductor layer
93
. Thus, according to conventional techniques, problematic propagation of dislocations cannot be prevented during formation of Group III nitride compound semiconductor layers.
The present invention has been accomplished in an attempt to solve the aforementioned problems, and an object of the present invention is to fabricate a Group III nitride compound semiconductor with suppressed generation of threading dislocations.
In order to attain the aforementioned object, the invention drawn to a first feature provides a method for fabricating a Group III nitride compound semiconductor through epitaxial growth, which comprises using a mask, etching an underlying layer comprising at least one layer of a Group III nitride compound semiconductor, the uppermost layer of the underlying layer being formed of a first Group III nitride compound semiconductor, to thereby form an island-like structure, such as a dot-like, stripe-shaped, or grid-like structure, and epitaxially growing, vertically and laterally, a second Group III nitride compound semiconductor not grown on the mark epitaxially, with the mask remaining on the upper surface of the uppermost layer in the underlying layer of the trench and with a sidewall of a trench serving as a nucleus for epitaxial growth, the post and the trench being formed by etching the first Group III nitride compound semiconductor so as to form an island-like structure such as a dot-like, stripe-shaped, or grid-like structure. In the present specification, the term “underlying layer” is used so as to collectively encompass a Group III nitride compound semiconductor single layer and a multi-component layer containing at least one Group III nitride compound semiconductor layer. The second Group III nitride compound semiconductor layer which “not grown on the mask epitaxially” means that the second Group III nitride compound semiconductor layer hardly grows on the mask. Practically, it may be sufficient that the mask be covered by lateral epitaxial growth (ELO). The expression “island-like structure” conceptually refers to the pattern of the upper portions of the posts formed through etching, and does not necessarily refer to regions separated from one another. Thus, upper portions of the posts may be continuously connected together over a considerably wide area, and such a structure may be obtained by forming the entirety of a wafer into a stripe-shaped or grid-like structure. The sidewall/sidewalls of the trench refers not only to a plane vertical to the substrate plane and the surface of a Group III nitride compound semiconductor, but also to an oblique plane. The trench may have a V-shaped cross-section with no flat surface on the bottom of the trench. Unless otherwise specified, these definitions are equally applied to the below-appended claims.
The invention drawn to a second feature provides a method for fabricating a Group III nitride compound semiconductor wherein the underlying layer is formed on the substrate and the etching is carried out until the substrate is exposed.
The invention drawn to a third feature provides a method for fabricating a Group III nitride compound semiconductor according to the invention as recited in connection with the first feature, wherein the depth and the width of the trench are determined such that lateral growth from the sidewall/sidewalls for covering the trench proceeds faster t
Hiramatsu Toshio
Koike Masayoshi
Kojima Akira
Tezen Yuta
Hoang Quoc
McGinn & Gibb PLLC
Nelms David
Toyoda Gosei Co,., Ltd.
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