Method for producing gate overlapped lightly doped drain (GOLDD)

Details Method for producing gate overlapped lightly doped drain (GOLDD) Method for producing gate overlapped lightly doped drain (GOLDD)

1991-09-10

1993-07-13

Quach, T. N.

Fishing, trapping, and vermin destroying

437200, 437239, H01L 21335

Patent

active

052273202

ABSTRACT:
A method produces a transistor with an overlapping gate. A first gate region is placed on a substrate between two source/drain regions. The first gate region includes a polysilicon region on top of a dielectric region. Gate overlap regions are placed around the polysilicon region. The gate overlap regions extend out over the two source/drain regions. The gate overlap regions are formed of a metal-silicide layer, for example Titanium-silicide. A top portion of the metal-silicide layer is oxidized to form a silicon dioxide layer on top of the metal-silicide layer. At the time of oxidation, the metal-silicide layer is also annealed to which further helps to improves the Titanium-silicide stoichiometry.

REFERENCES:
patent: 4567058 (1986-01-01), Koh
patent: 4716131 (1987-12-01), Okazawa et al.
patent: 4971922 (1990-11-01), Watabe et al.
patent: 5003375 (1991-03-01), Ichikawa
Wolf, S., et al., Silicon Processing, vol. 1, Process Technology, pp. 384-399, 1986, Lattice Press.
J. E. Moon, et al., "A New LDD Structure: Total Overlap with Polysilicon Spacer (TOPS)", IEEE Electronic Device Letters, May 1990, pp. 221-223.
T. Y. Huang: "A novel SubMicron LDD Transistor with Inverse-T Gate Structure", IEDM, 1986, pp. 742-745.
R. Izawa, et al., "The Impact of Gate-Drain Overlapped LDD (GOLD) For Deep SubMicron VLSIs", IEDM 1987, pp. 38-41.

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