Adhesive bonding and miscellaneous chemical manufacture – Methods – Surface bonding and/or assembly therefor
Reexamination Certificate
1998-11-02
2001-08-07
Mayes, Curtis (Department: 1734)
Adhesive bonding and miscellaneous chemical manufacture
Methods
Surface bonding and/or assembly therefor
C156S089170, C156S089180, C156S252000, C156S272800, C156S293000, C427S097100
Reexamination Certificate
active
06270601
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for filling holes in substrates and the resulting products. More particularly, the present invention relates to a method for producing filled vias in ceramic substrates to obtain electronic components.
2. Description of Related Art
The production of filled vias in insulating substrates is an important part of the electronics industry. A particular desirable embodiment includes electrically conductive metal vias formed in electrically insulative ceramic substrates. These substrates can be employed in a number of electronic components. Prior electronic devices have been produced using ceramic substrates, wherein each substrate has a particular screened metal pattern on its planar surface and a selected pattern of feed-through vias, or holes, formed through the sheet. The vias in the ceramic sheets are usually filled in the unfired or “green” state with a slurry of refractory metal paste, i.e., tungsten particles suspended in an organic vehicle. Screen printing techniques, through either a stencil or a screen, are typically used to apply the planar metallization and to force the metallizing paste into the vias.
During the sintering operation, the binder is volatilized from the ceramic sheet, the patterned metallization and the via metallization. After binder removal, the temperature is increased to provide densification by sintering of the ceramic and refractory metal portions of the assembly. The metal-filled vias then become electrical conductors and provide selective electrical interconnection between the various locations on the device.
While most vias in an electronic device are designed to provide electrical interconnection, vias may also be provided to function as thermal pathways for heat generating components that are placed within or on top of the device. Vias can also be included to function as electrical grounds for the components.
One of the drawbacks of screening metals into vias and conductor paths is that the metal pastes represent a significant cost to the manufacturer of the electronic component. Further, metal pastes often contain many volatile organics and other environmentally undesirable constituents that are used to adjust the rheology of the paste. Moreover, the metallized ceramic device must be sintered in a non-oxidizing atmosphere to avoid oxidation of the refractory metal and the vias usually are not dense.
Some techniques have been developed to address one or more of these problems. U.S. Pat. No. 4,942,076 by Panicker et al., issued Jul. 17, 1990, discloses a single-layer ceramic substrate with metal-filled vias that is useful for mounting high-frequency hybrid microcircuits. Panicker et al. use a screening process to place a refractory metal (e.g., tungsten) and binder into vias that are formed in ceramic sheets and then sinter the sheets such that the tungsten-filled vias have 10 to 20 percent porosity. Copper is then screened onto the porous tungsten-filled vias and the sheets are heated in a reducing atmosphere to reflow the copper into the tungsten. The result is a ceramic substrate having a plurality of vias filled with about 85% tungsten and about 15% copper. It is disclosed that the vias are useful for ground connections and for carrying away internally generated heat.
U.S. Pat. No. 5,089,881 by Panicker issued on Feb. 18, 1992, discloses a ceramic-based chip carrier for mounting an IC chip wherein certain vias in the ceramic substrate include a porous refractory metal that has copper metal reflowed into the porosity of the refractory metal. In the process for making the chip carrier, a sintered ceramic substrate is laser-drilled to form vias therein and the vias are thereafter filled with a refractory metal paste and fired in a reducing atmosphere to sinter the refractory metal into a porous mass. Copper is then screened onto the refractory metal-filled vias and is then heated in a reducing atmosphere to reflow the copper into the porous metal. At least three furnace cycles are required. This process is also not a co-fire process wherein the refractory metal and the ceramic are sintered in a single step.
U.S. Pat. No. 5,163,499 by Newkirk et al., issued on Nov. 17, 1992, discloses a method of forming electronic packages by infiltrating a permeable mass of filler material or a preform with molten matrix metal and bonding the infiltrated material to a second material, such a ceramic or metal. Prior to infiltration the filler material or preform is in contact with a portion of the second material such that after infiltration, the infiltrated material is bonded to the second material to form a sealed electronic package.
U.S. Pat. No. 5,614,043 by Ritland, et al. issued on Mar. 25, 1997 relates to ceramic-based electronic components wherein a portion of the component comprises a metal-infiltrated ceramic. In particular, copper infiltrated ceramic vias are disclosed. The vias are filled with a porous sintered ceramic which is subsequently infiltrated with a molten metal, such as copper. U.S. patent application Ser. No. 08/820,164 filed Mar. 19, 1997 and entitled “Electronic Components Incorporating Ceramic-Metal Composites” by Ritland, et al. is a continuation of U.S. Pat. No. 5,614,043. U.S. patent application Ser. No. 08/949,227 filed Oct. 13, 1997 and entitled “Electronic Components Incorporating Ceramic-Metal Composites” by Ritland, et al., now U.S. Pat. No. 6,143,421, is a continuation-in-part based on, among others, U.S. Pat. No. 5,614,043. Each of U.S. Pat. No. 5,614,043 and U.S. patent application Ser. Nos. 08/820,164 and 08/949,227, now U.S. Pat. No. 6,143,421, are incorporated by reference herein in their entirety.
There exists a need for a method that is useful for forming high-conductivity vias, conductor paths, ground planes and other components on insulating substrates. It would be desirable for the vias to be filled with a highly conductive material, such as silver or copper. It would be advantageous if vias could be easily formed having a high conductivity metal. It would be advantageous if the components could be sintered and/or at least partially fired in a non-reducing atmosphere. It would also be advantageous if an efficient and flexible production process could be used to form the components.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, a product, preferably an electronic component, is provided which includes a substrate with at least one hole which extends through the substrate and a multicomponent material filling the hole. The multicomponent material includes at least two components. The first component, when melted, is capable of wetting both the substrate and the molten second component. The second component is conductive and also bonds with the first component, which bonds with the substrate. Preferably, the first component is located between the walls of the hole and the second component in order to provide effective bonding.
The substrate is preferably a ceramic material such as alumina, zirconia, aluminum nitride, beryllia, silicon carbide, magnesia, silicon nitride and mullite. The first component is preferably a metal oxide such as a copper oxide and the second component is preferably a conductive material such as silver or copper.
The hole or holes in the substrate are preferably from about 2 mils to about 50 mils in diameter and can have any suitable cross sectional geometry such as round, oval, slotted, star-shaped, chevron, polygonal and irregular. The substrate is preferably from about 3 mils to about 60 mils in thickness and the ratio of the thickness of the substrate and the average diameter of the holes in the substrate is preferably from about 0.5:1 to about 50:1. Preferably the first component is from about 0.5 mole percent to about 25 mole percent of the total amount of the multicomponent material. In a preferred embodiment at least one surface of the product is treated to provide a flat, smooth surface.
According to another embodiment of the present invention, a method for making
Landin Steven M.
Ritland Marcus A.
Coorstek, Inc.
Mayes Curtis
Sheridan & Ross P.C.
LandOfFree
Method for producing filled vias in electronic components does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for producing filled vias in electronic components, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for producing filled vias in electronic components will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2438002