Method for producing conducting layers for a semiconductor devic

Details Method for producing conducting layers for a semiconductor devic Method for producing conducting layers for a semiconductor devic

1992-10-30

1994-11-22

Thomas, Tom

Fishing, trapping, and vermin destroying

437173, 437174, 437188, 437982, H01L 2100

Patent

active

053669053

ABSTRACT:
A thermal planarization method of a surface of conducting layers for interconnects in high-density integrated circuits. When a conducting layer having an insulating layer with steps or grooves underneath is heated in a vacuum chamber, the surface is irradiated by an energy beam such as a He-Ne laser and a change of the reflective intensity followed by melting or planarizing of the conducting layer is monitored in real time basis, in situ. The monitored signal is electrically fed back quickly to a temperature controller to control a heating condition so that failure in planarizing a conducting layer due to insufficient heating, or coagulation or even evaporation of the layer due to excessive heating can be avoided.

REFERENCES:
patent: 4431900 (1984-02-01), Delfino et al.
patent: 4902631 (1990-02-01), Downey et al.
patent: 5104482 (1992-04-01), Monkowski
patent: 5169800 (1992-12-01), Kobayashi

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