Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2007-09-18
2007-09-18
Dang, Phuc T. (Department: 2818)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C257S620000
Reexamination Certificate
active
11079620
ABSTRACT:
The method of the present invention relates to a method for producing a chip stack comprising the steps of manufacturing at least a first and a second integrated structure on a single substrate, an area of the first integrated structure and an area of the second integrated structure adjoining a respective first and second kerf area; providing a first redistribution layer on the first integrated structure on the substrate, said first redistribution layer at least partially extending beyond the area of the first integrated structure into the first kerf area, thereby forming a first integrated device area, wherein a first contact pad is arranged on the first redistribution layer in a first contacting area overlapping the first kerf area; providing a second redistribution layer on a second integrated structure on the substrate, including a second contact pad, thereby forming a second integrated device area; separating the first and second integrated device areas along a separation line defined by at least one of the boundaries of the first integrated device area and the second integrated device area, resulting in separated first and second integrated devices; and stacking the second integrated device on the first integrated device so that the first contacting pattern is uncovered by the second integrated device.
REFERENCES:
patent: 2005/0139985 (2005-06-01), Takahashi
patent: 2005/0179127 (2005-08-01), Takyu et al.
patent: 2006/0157866 (2006-07-01), Le et al.
patent: 2006/0202317 (2006-09-01), Barakat et al.
Dang Phuc T.
Infineon - Technologies AG
Patterson & Sheridan L.L.P.
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