Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
2000-06-01
2002-04-23
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S255000, C257S296000, C257S309000
Reexamination Certificate
active
06376328
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates to a method for producing capacitor elements, and a capacitor element. In particular, the invention is directed at a method for producing capacitor elements, which enables improved operating reliability of capacitor elements.
2. Description of the Related Arts
Recently, in order to increase the capacitance of a capacitor element that constitutes a semiconductor device, for example, a DRAM (Dynamic Random Access Memory), a technology (HSG technology), which forms an HSG (Hemispherical Grain) in a lower electrode of a capacitor element, has been frequently employed.
In the HSG technology, thermal processing is applied to an amorphous silicon layer in a vacuum state to migrate silicon atoms, and an HSG is formed on the film surface, whereby the surface area of the lower electrode is increased, resulting in an increase in the capacitance of a capacitor element.
In the HSG technology, there are mainly two types of method, one of which is a blanket HSG method, and the other of which is a selection HSG method.
In the blanket HSG method, an amorphous silicon layer is formed in an LP-CVD (Low Pressure Chemical Vapor Deposition) furnace, thereby forming an HSG. In detail, the pressure in the LP-CVD furnace is set to, for example, 0.2 Torr or so, and the temperature is set to, for example, a transition temperature or so between amorphous and crystal, wherein a silane gas or a disilane gas is introduced into the furnace to form a silicon layer. After the silicon layer is formed, the supply of silane gas is stopped, wherein annealing is carried out for several minutes with a vacuum inside the furnace. And, silicon atoms are migrated to form an HSG on the film surface.
On the other hand, in the selection HSG method, an amorphous silicon layer is formed in advance and patterning is applied thereto. Natural oxide films and organic substances existing on the surface of the film are removed to clean the surface. Thereafter, an HSG is formed on the surface of an amorphous silicon layer, using an LP-CVD furnace, etc. In detail, the pressure inside the LP-CVD furnace is set to, for example, 1mTorr or so, and a silane gas is irradiated on the clean surface of the amorphous silicon layer, whereby micro crystals which become the growth nuclei of HSG are formed on the surface of the amorphous silicon layer. After that, the supply of silane gas is stopped, and the amorphous silicon layer containing micro crystals is annealed in a state where the pressure inside the furnace is kept on 1×10
−7
Torr or less, whereby silicon atoms are migrated to form an HSG on the film surface.
Also, even though either technology of the abovementioned blanket HSG method or the selection HSG method is employed, the HSG just after being formed includes almost no impurities. That is, almost no carrier is included in the just formed HSGs. Where almost no carrier exists in an electrode of a capacitor element, the capacitance is lowered due to depletion of the electrode.
One of the methods for diffusing impurities in the HSG is a method of injecting impurities from outside an HSG. For example, after an HSG is formed on the surface of a silicon layer, thermal processing is carried out at 700° C. in the atmosphere of POC13 (phosphorus oxytrichloride), using an LP-CVD furnace, etc. As described above, by thermally processing in the atmosphere of POC13, impurities can be sufficiently diffused in the HSG. But, the POC13 forms a smooth phosphorus glass film on the HSG surface by reaction with silicon contained in the HSG. The phosphorus glass film fills up clearance between the HSGs, resulting in a lowering of the surface area of the lower electrode. Therefore, the phosphorus glass film on the HSG surface must be removed by using fluoric acid, etc. However, since the phosphorus glass film is formed by a chemical reaction with silicon, there arises a problem by which the size of the HSG is made very small or some HSGs are omitted by removing the phosphorus glass film.
In addition the above description, technologies for diffusing impurities in HSGs are disclosed by Japanese Laid-Open Patent Publication Nos. 70249 of 1998 and 303368 of 1998.
In the technology disclosed in Japanese Laid-Open Patent Publication No. 70249 of 1998, impurities are injected into the HSGs by using an ion injection method after HSGs are formed on a silicon layer surface.
In the technology disclosed in Japanese Laid-Open Patent Publication No. 303368 of 1998, after HSGs are formed on a silicon layer surface, natural oxide films and contaminated substances on the surface of the HSGs are removed by using a wet type detergent such as a hydrogen fluoride acid solution and BOE (Buffer oxide etching solution), etc. Thereafter, impurities are diffused in the HSGs, using an LP-CVD apparatus and RTP (Rapid Thermal Processing) apparatus. In detail, in the case where an LP-CVD apparatus is used, thermal processing is carried out at 650 through 850° C. in an atmosphere of phosphine (PH3) to cause phosphorus to diffuse in the HSGS. On the other hand, in the case where the RTP apparatus is used, thermal processing is carried out at 550 through 900° C. in an atmosphere of phosphine to cause phosphorus to diffuse in the HSGS. In detail, in the LP-CVD apparatus, thermal processing is carried out at 700° C. for three hours and, in the RTP apparatus, thermal processing is carried out at 800° C. for 300 seconds.
In Japanese Laid-Open Patent Publication No. 303368 of 1998, such a technology has been disclosed, in which phosphine exited by plasma discharge is irradiated on HSGs for annealing in order to diffuse impurities in the HSGs.
However, the technologies disclosed in Japanese Laid-Open Patent Publication Nos. 70249 of 1998 and 303368 of 1998 described above still have the-following problems.
In the technology disclosed in Japanese Laid-Open Patent Publication No. 70249 of 1998, it is difficult to uniformly irradiate ions on the upper and lower parts of a cylinder type lower electrode, in particular, on a lower electrode having a high aspect ratio. Besides, if the energy for injection of ions is increased to dope sufficient impurities on the lower part of the lower electrode, there may arise such a problem by which the HSGs may collapse or be missed.
In Japanese Laid-Open Patent Publication No. 303368 of 1998, it has been found that a hold defect (an error caused when an electric charge cannot be maintained sufficiently long) frequently occur when making practical operations. Based on the results of analysis made by the present inventors, etc., the hold defect arises when water marks and natural oxide films exist in a minute area of the lower electrode having HSGs, and impurities are not sufficiently diffused in the lower electrode (HSG). Such water marks and natural oxide films remain when cleaning the HSG surface with a wet type detergent or may be formed in a drying process after cleaning. This is liable to occur after the HSGs are formed, and it is considered that it results from the shape thereof.
Also, recently, there are cases where a semiconductor device is constructed by the mixed of mounting DRAMs and logic circuits on the same chip. In a logic circuit production process, since a salicide (self-align silicide) process resides in a process-for producing logic circuits, the thermal allowance (amount of thermal load applied) is decreased in the process for producing DRAMs. In detail, in the case where a normal furnace is used, the thermal processing temperature must be 600° C. or less. And in the case where the RTP apparatus is used, processing at 800° C. or so for several minutes in total may be allowable.
In the technology disclosed by Japanese Laid-Open Patent Publication No. 303368 of 1998, where an LP-CVD apparatus is used, thermal processing is carried out at 700° C. for three hours. Therefore, the temperature exceeds the abovementioned thermal allowance in the process of formation of a lower electrode. On the other hand, where an RTP apparatus is used, therma
Aiso Fumiki
Hirota Toshiyuki
Blum David S
Bowers Charles
NEC Corporation
Rosenman & Colin LLP
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