Method for producing an SOI wafer

Details Method for producing an SOI wafer Method for producing an SOI wafer

1999-12-08

2003-01-14

Mulpuri, Savitri (Department: 2812)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S435000

Reexamination Certificate

active

06506663

ABSTRACT:

TECHNICAL FIELD
The present invention relates to an improved method for producing a silicon-on-insulator (SOI) wafer.
BACKGROUND OF THE INVENTION
As known, according to widespread practice in the microelectronics industry, the substrate of integrated devices is obtained from wafers of monocrystalline silicon. In the last few years, as an alternative to wafers consisting of silicon alone, composite wafers, so-called “SOI” (Silicon-on-Insulator) wafers have been proposed, comprising two silicon layers, one of which is thinner than the other, separated by a silicon oxide layer.
A method for producing SOI wafers is the subject of European patent application no. 98830007.5 filed on Jan. 13, 1998 for the same applicant, and is described hereinafter with reference to
FIGS. 1-9
.
According to this method, and referring to the figures, on a surface
3
of a monocrystalline silicon region
2
, initially a first silicon oxide layer is grown, having a thickness for example comprised between 200 and 600 Å; a first silicon nitride layer having a thickness comprised between 900 and 1500 Å is then deposited. Using a resist mask, dry etching is carried out of the uncovered portions of the first oxide layer and the first nitride layer, and the resist mask is then removed, providing the intermediate structure of
FIG. 1
, wherein the wafer thus obtained is shown at 1, and the portions of the first oxide layer and the first nitride layer remained after dry etching, are indicated at 4 and 5 and define respective first protective regions
7
, covering first portions
8
′ of monocrystalline silicon region
2
.
The first protective regions
7
form a hard mask, indicated at
9
and are used to etch the monocrystalline silicon region
2
at the second portions
8
″ left uncovered by the mask
9
, such as to form initial trenches
10
(FIG.
2
), having a depth comprised between 0.5 and 5 &mgr;m, depending on the desired characteristics of the buried oxide layer to be produced.
Subsequently, as shown in
FIG. 3
, the wafer
1
is subjected to oxidation, to form a second oxide layer
11
, having a thickness, e.g. comprised between 200 and 600 Å, and covering the lateral and base walls
10
a,
10
b
of the initial trenches
10
, and a second silicon nitride layer
12
having a thickness comprised between 900 and 1500 Å is then deposited.
Subsequently, layers
12
and
11
are anisotropically etched without a mask. Owing to the etching anisotropy, the horizontal portions of the second silicon nitride layer
12
and the oxide layer
11
, on the base walls
10
b
of the initial trenches
10
and on the portions
4
and
5
, are removed, thus providing the intermediate structure of FIG.
4
. The regions
8
′ are still covered on top by the mask
9
, and laterally (on the vertical walls
10
a
) by oxide and nitride portions
11
′ and
12
′; on the other hand, the monocrystalline silicon region
2
is bare on the base wall IOb of the initial trenches
10
.
The uncovered silicon, at the base wall
10
b
of the initial trenches
10
is etched, to deepen the initial trenches
10
, obtaining final trenches
16
having a required depth. In particular, the depth of the final trenches
16
(like that of the initial trenches
10
) determines the dimensions of the desired covered oxide layer, and thus the electrical characteristics of the SOI wafer, as explained hereinafter, and is thus selected according to the specifications provided for the final SOI wafer.
The monocrystalline silicon region now comprises a base portion shown at
2
′, and a plurality of “columns”
18
, extending vertically from the base portion
2
′. Thus the intermediate structure of
FIG. 5
is obtained, wherein the nitride portions
5
and
12
′ are no longer separate from each other, and are indicated at
19
, and the oxide portions
4
and
11
′ are also no longer separate from each other, and are indicated at
20
and, with the portions
19
, form second protective regions
30
.
A thermal oxidation step is then carried out, thereby the exposed silicon regions of the “columns”
18
are transformed into silicon oxide. In practice, the oxide regions gradually grow from the silicon regions, from the lateral walls of the final trenches
16
towards the interior of the columns, and partially also towards and inside the base portion
2
′. Since during the oxidation the volume increases, the oxide regions that are being formed gradually, occupy the space of the final trenches
16
, until they close the latter completely, and are joined to one another. The oxidation step ends automatically once the columns
18
have been completely oxidized (apart from the upper area or tip, indicated at
21
, which is protected by the second protective regions
30
), thus forming a continuous buried oxide region
22
, shown in
FIG. 6
, wherein continuous vertical lines show meeting surfaces of the oxide regions being formed from walls of two final adjacent trenches
16
, showing the oxide expansion.
Subsequently, by selective etching, the second protective regions
30
are removed and uncover the “tips”
21
, which are designed to form the nuclei for a subsequent epitaxial growth.
The structure of
FIG. 7
is obtained, showing the three-dimensional structure of the wafer I in this step. Subsequently, epitaxial growth is carried out, the parameters whereof being selected to avoid silicon nucleation in the areas above the buried oxide region
22
, and to have a high ratio of lateral to vertical growth, to obtain first horizontal growth of silicon around the tips
21
(thus covering the upper surface of the buried oxide region
22
), and then vertical growth of an epitaxial layer
23
. After an optional step of chemical/mechanical polishing to level the upper surface of the wafer
1
, the final structure of the wafer
1
, shown in
FIG. 8
, is then obtained.
Thereby it is possible to produce an SOI wafer using only process steps common in microelectronics, with far lower costs than those of the processes used now for production of SOI substrates.
However, the above-described production method has the disadvantage that during the step of non-masked anisotropic etching, there are uncovered oxide portions, which, during the subsequent epitaxial step, produce extensive areas rich in crystallographic defects.
In particular, as illustrated in greater detail in
FIG. 9
, relative to a single initial trench, the second oxide layer grows, inter alia, towards the interior of the initial trench
10
, forming steps
39
. Consequently, when subsequently depositing the second silicon nitride layer
12
, the latter follows the inner profile of the lateral walls of the initial trenches
10
, and thus in turn forms a pair of steps
40
in each initial trench
10
.
The presence of these steps
39
,
40
means that in the subsequent step of non-masked anisotropic etching of the layers
12
and
11
, not only the horizontal portions of the second silicon nitride
12
and oxide
11
layers are removed on the base of the initial trenches
10
, and above the portions
4
and
5
, but also the portions of the second silicon nitride layer
12
which form the steps
40
, thus leaving uncovered the portions of the second oxide layer
11
′ defining the steps
39
, as illustrated in FIG.
10
.
Consequently, in the subsequent oxidation step for growing the buried oxide region
22
, silicon oxide is grown at the steps
39
, forming oxide areas
41
(FIG.
11
). These oxide areas
41
cause the formation, in the subsequent epitaxial growth, of extensive areas rich in crystallographic defects in the epitaxial layer
23
, which areas are delimited by broken lines in FIG.
12
.
SUMMARY OF THE INVENTION
The present invention improves the above-described method so as to eliminate the crystallographic defects present in the epitaxial layer and to obtain improvement of the electrical characteristics of the SOI wafer.
According to the disclosed embodiments, a process for producing a wafer includes forming a protective

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