Method for producing an integrated circuit structure with a dens

Details Method for producing an integrated circuit structure with a dens Method for producing an integrated circuit structure with a dens

1991-07-17

1992-04-28

Wojciechowicz, Edward J.

Fishing, trapping, and vermin destroying

357 52, 357 71, 437198, 437235, 437978, 437985, H01L 2934, H01L 2144

Patent

active

051092670

ABSTRACT:
Disclosed is a method for manufacturing a high-denisty multilayer metallization pattern on an integrated circuit structure. Also disclosed are integrated circuit structures made with such method. The components of the integrated circuit may be formed on the substrate using conventional processes. A first metallization pattern is then formed on the semiconductor substrate having at least one integrated circuit. Next, the first layer of a double-layer insulation is applied over the first metallization pattern, and a photoresist layer is applied over the first layer for planarizing the topology of the metallization pattern and for defining a pad mask by a photoprocess over a conductive pad. For planarization of the topology, the photoresist layer and the first layer of the double-layer insulation are reactive ion etched at substantially the same rate to a desired depth. This reactive ion etching step also removes the first layer of the double-layer insulation from the pad mask area thereby exposing a metal pad. On top of the planarized topology, the second layer of the double-layer insulation is applied, and vias are opened in the layer by a plurality of dry-etching steps. The second metalliation pattern is formed on this second layer. Then, another double-layer insulation is applied on top of the second metallization pattern, the first layer being an inorganic and the second layer an organic layer. After opening vias in the layers of this double-layer insulation by contour-etching, a third metallization pattern is applied. Optionally, a fourth metallization pattern can be formed on the integrated circuit structure.

REFERENCES:
patent: 5060050 (1991-10-01), Tsuneoka et al.

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