Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates – Thinning of semiconductor substrate
Reexamination Certificate
2001-08-15
2003-06-24
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Bonding of plural semiconductor substrates
Thinning of semiconductor substrate
C438S455000, C438S462000, C438S464000, C257S679000, C257S698000, C257S773000, C257S774000
Reexamination Certificate
active
06583030
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a method for producing an integrated circuit processed on both sides, to a circuit produced by said method and to a module and a smart card having a thus produced circuit.
A particular problem in the production of integrated circuits in general is the wiring, which is becoming ever more complex given ever smaller structural widths and greater functionality. This means that the metalization is effected in a plurality of layers in the wiring of the chips, or the number of layers increases constantly with rising chip complexity. The difficulty arises that only a limited number of metalization layers may be disposed one on the other.
The prior art discloses vertically integrated circuits. Vertical system integration provides a method by which a chip or wafer is thinned and bonded to another chip or wafer. A method for producing a three-dimensional integrated circuit is known for example from German laid open print DE-OS 44 33 845. This is a method by which two finished substrates provided with metalization structures are interconnected. The thinned wafers are diced into individual chips and applied to the lower substrate, at least one of the substrates being subjected to a functional test before the substrates are joined for eliminating faulty chips. The metalization structure of the lower wafer is connected with the component level of the upper wafer so as to provide an integrated circuit with two or more independently produced chips.
The disadvantage of said methods is that every metalization structure is associated with a circuit structure and high alignment accuracy is required when the structures are joined or high reject rates must be accepted.
SUMMARY OF THE INVENTION
It is therefore the problem of the invention to state a method which permits wiring with reasonable effort and low reject rates even for complex integrated circuits, and to state an integrated circuit produced by said method.
This problem is solved by a method and an integrated circuit according to the present invention. Advantageous embodiments of the invention are also provided.
The essence of the invention is that a finished wafer, i.e. a substrate with a circuit structure and a metalization structure disposed thereon and preferably consisting of a plurality of layers, is rebonded to a handling wafer after the structure has been provided with plated-through holes to the wafer backside which have been insulated against the silicon. After rebonding, the first substrate is thinned from the backside so that the plated-through holes are open and the metalized connections are exposed. A second metalization structure is now produced on the chip backside and connected with the first metalization structure by means of the throughplating.
With the inventive method one can produce an integrated circuit wherein a circuit structure is provided with a metalization structure on both sides. Due to the direct processing on the thinned circuit structure the effort for positioning is no higher than with conventional one-sided metalization. This makes it possible to provide wiring even for very small structural widths, or permits such wiring.
One obtains even more exact alignment and thus a further reduction of the reject rate for the second metalization structure by etching alignment marks which are recognizable from the backside before thinning the substrate or before rebonding to the carrier wafer.
In order to avoid separate method steps for etching the alignment marks and the plated-through holes, it is advantageous to etch the plated-through holes and the alignment marks in the same method step.
Further, it has proved advantageous to metalize the plated-through holes before thinning. In this way the thinning process can be ended when the metalization of the plated-through holes is reached. Alternatively, metalization can be performed after the thinning process, in which case the thinning process is ended when the plated-through holes are reached.
When applying metalization structures on both sides for the wiring, one may further utilize the possibility for different security-relevant applications of protecting the chip from both sides with a metalization level serving as a intrusion detection screen. In this way one can produce a safe chip without requiring additional method steps for applying the intrusion detection screen.
For more extensive circuit structures it makes sense to use as the first wafer a substrate with a buried oxide layer, said oxide layer having an insulating effect so that it is possible to apply a circuit structure to both sides of the oxide layer. The backside of the substrate can be thinned after the method step of rebonding to the first handling wafer, a second circuit structure then being processed on said backside. Subsequent to the processing of the second circuit structure one can advantageously continue with the processing of the metalization structure. Subsequent to the processing of the metalization structure the wafer is planarized on the backside and rebonded to a second handling wafer so that one can continue with the processing of a metalization structure on the first circuit structure. This is necessary when the substrate with the buried oxide layer was not already provided with a metalization structure on the first circuit structure at the beginning.
In the structure with a buried oxide layer the plated-through holes are advantageously etched through and metalized before rebonding to the first handling wafer.
It should also be mentioned that in accordance with another advantageous embodiment of the invention the wafer processed on both sides can be connected with one or more further wafers processed on one or both sides to form a chip stack.
A circuit of the invention is provided by using the above-described method. Said circuit has a configuration wherein a one or multilayer metalization structure is disposed over the circuit structure and wherein a second metalization structure is further present below the circuit structure. The first and second metalization structures are interconnected by means of interchip connections.
The integrated circuit further has advantageous embodiments which result from the method steps. Thus, the integrated circuit can for example be provided on both sides with a intrusion detection screen; it can further contain a substrate with a buried substrate layer and thus two different circuit structures. Finally, the inventive integrate circuit can be stacked with further integrated circuits which are likewise processed on both sides or with one-sidedly processed circuits or wafers or chips.
A module is provided that is suitable for incorporation in a smart card and contains an integrated circuit of the invention.
A smart cart of the invention is provided that contains an integrated circuit or module.
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Bacon & Thomas PLLC
Giesecke & Devrient GmbH
Smith Matthew
Yevsikov V.
LandOfFree
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