Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2005-08-16
2005-08-16
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S624000, C438S634000, C438S637000, C438S700000, C438S734000
Reexamination Certificate
active
06930052
ABSTRACT:
In order to fabricate a metallization plane with lines and contacts, four dielectric layers are applied to a substrate. Firstly, contact holes are etched through the top two dielectric layers into the underlying dielectric layer, the remaining thickness of the latter layer being essentially equal to the thickness of the top layer. Line trenches are subsequently etched selectively with respect to the first dielectric layer and the third dielectric layer, whose surfaces are uncovered essentially simultaneously. After the first dielectric layer and the third dielectric layer have been patterned, contacts and lines are produced in the contact holes and line trenches.
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Engelhardt Manfred
Kreupl Franz
Schwarzl Siegfried
Altera Law Group LLC
Fourson George
Infineon - Technologies AG
Maldonado Julio J.
Stone Jeffrey R.
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