Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices
Reexamination Certificate
2002-11-01
2004-03-30
Martin, David (Department: 2841)
Electricity: electrical systems and devices
Housing or mounting assemblies with diverse electrical...
For electronic systems and devices
C361S728000, C361S729000, C361S784000, C361S790000, C257S686000
Reexamination Certificate
active
06714418
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to a method for producing an electronic component with a plurality of chips that are stacked one above the other and contact-connected to one another, which component can be mounted on a component carrier and can be contact-connected on the component carrier via a plurality of contact elements provided on the component.
Known methods for producing a component with a plurality of chips that are stacked one above the other into the third dimension can roughly be divided into two groups. One group is the stacking of housed chips, and the other group is the stacking of bare chips. When stacking housed chips, the latter are stacked one above the other and connected to one another by their contact elements, which may be small legs. Examples thereof are stacked TSOP or stacked BOC. These three-dimensional designs are distinguished by so-called interposers, which are thin or thick boards or leadframes, for connection between the stack planes. These interposers are mounted onto the chips and connected to the chip-side contact elements by suitable methods. This method is expensive on account of its mounting outlay, since it is based on a single-die process flow, for example, exclusively separate individual housed chips are processed. On account of the interposers that are necessary in part, the resulting components are of considerable structural height. It is not possible to thin down the chips during the stacking process on account of the housing that has already been effected.
By contrast, a component produced by stacking bare chips enables a smaller construction height. The chip-to-chip connection system leads through the respective chip. The fine contact-connecting vias required for this are usually produced in a front-end-like process, which includes via etching/passivation/via filling. However, this method has crucial disadvantages for the application. On the one hand, it presupposes a particular chip design which allows the production of contact-connecting or through vias. The vias are very expensive to produce since they have to be produced in an additional, relatively long process sequence of front-end processes. Although the essential processes can be carried out at the wafer level, difficulties with regard to the yield nonetheless arise when stacking bare chips at the wafer level. Since each wafer only has a finite yield of functioning chips, when stacking the wafers the risk is exponentiated for a functioning stack, and the yield decreases exponentially with an increasing number of stacked wafers. Economic component production by this method is not possible.
SUMMARY OF THE INVENTION
The invention is based on a task of providing a method which makes it possible to produce components of relatively low construction with a high yield in a simple manner.
In order to solve this task, the invention provides a method of the type mentioned in the introduction having the following steps:
a) producing a first planar chip arrangement by arrangement of functional chips spaced apart from one another in a grid and filling at least the spacings between the chips with a filling agent for the purpose of forming an insulating holding frame that fixes the chips with chip-dedicated contact-connecting elements that serve for the electrical contact-connection to another chip of another chip arrangement and are provided in the region of the holding frame, and chip-dedicated rewiring,
b) producing and/or arranging of a further planar chip arrangement according to step a) on the first chip arrangement in such a way that the chips and the holding frames of the two chip arrangements lie one above the other and the respective contact-connecting elements of the two chip arrangements are connected to one another for the electrical chip-to-chip contact-connection to form joined-together components,
c) if appropriate single or multiple repetition of step b), and
d) separating the joined-together components each comprising a plurality of chips of the individual chip arrangements, which chips are stacked one above the other, by separation of the holding frames of the chip arrangements that are fixedly connected to one another.
The method according to the invention firstly proposes the production of a wafer comprising exclusively chips that have been tested as functional in a previous test. This so-called “known good wafer” is produced by positioning the chips in a grid fashion and correspondingly embedding said chips in an insulating holding frame, which is preferably produced by means of a viscous non-conductive polymer used as a filling agent. In this case, it is conceivable to integrate into this wafer either identical chips or else different chips which differ in their properties and/or dimensions. This wafer or this first planar chip arrangement is thus produced by a fan-out wafer-level packaging. This holding frame for the fan-out wafer-level packaging is now not only utilized for fan-out, rather it also serves to form the through-platings from the chip front side to the chip rear side i.e. the through-plating is displaced to the holding frame region. Afterward, a further chip arrangement is then produced in this way, that is to say stacked on, the chips and the holding frames being positioned congruently above one another, if the multichip stack is constructed from identical or identically sized chips. However, it is also possible to arrange different or differently sized chips in the individual planes, in which case the congruent stacking one above the other is not always possible on account of the differences in size. The abovementioned step is repeated as many times as separate chip layers are to be provided. Once all the chip layers have been stacked one above the other, the individual components are singulated by separation of the stack in the region of the holding frame.
The method according to the invention has appreciable advantages over the known methods. First, it is a complete wafer-level process, since the work is effected at the wafer level and the singulation is carried out only after the components have been produced in their entirety by formation of the stack. Since exclusively functional chips are used, the yield is very high. All standard chips can be used, and it is possible to integrate identical or different chips in each plane. Furthermore, it is a very cost-effective process, since the contact vias for the contact-connections do not have to be led through the conductive silicon crystal with expensive technology, but rather through the holding frame, which can be carried out using significantly simpler thin-film and/or thick-film processes. Furthermore, a process sequence which can be carried out at very low process temperatures of less than 150° C. is. involved, which does not result in additional loading on the chips. Moreover, the stacking of the chips or wafers, which are de facto bare, permits the production of components with an extremely small structural height, and results in a very low risk with regard to handling and breakage during production.
The method according to the invention makes it possible to construct a multichip arrangement without the mounting of an additional object, for example an interposer. Rather, in this case the chip arrangements are placed or constructed directly on top of one another. The wiring of the chips is effected directly at the wafer level, which is to say directly in the plane of the wafer, and the wiring strip or conductive paths can be processed using wafer level technology, which includes thin film/thick film. This is made possible by the holding frame which in each case surrounds a chip and serves as a contact-connecting region, for example, the electrical chip-to-chip contact-connection and also the connection to the module board is effected in the region of the holding frame. In addition to a minimum of required contact transitions, both mechanical and above all electrical, a multichip component produced in this way is also distinguished by its low structural height and the small late
Frankowsky Gerd
Hedler Harry
Irsigler Roland
Meyer Thorsten
Vasquez Barbara
Infineon - Technologies AG
Levi Dameon E.
Martin David
Schiff & Hardin LLP
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