Fishing – trapping – and vermin destroying
Patent
1989-07-19
1991-09-03
Chadhuri, Olik
Fishing, trapping, and vermin destroying
437101, 357 237, H01L 213205, H01L 21283
Patent
active
050454854
ABSTRACT:
A method for producing an amorphous silicon thin film transistor array substrate comprising successively coating a gate insulating layer, an amorphous silicon layer and a protective insulating layer on a glass substrate provided with a gate electrode and a gate wiring having a predetermined shape, in such a manner as to not cover the connecting terminal region of the gate wiring. A protective insulating layer is patterned into a predetermined shape. After passing through a predetermined production process to produce an amorphous silicon thin film transistor array, at least a gate wiring and a source wiring are provided. The step of patterning the protective insulating layer comprises covering the connecting terminals of the gate wiring and the exposed region of the glass substrate with a photoresist.
REFERENCES:
patent: 4601097 (1986-07-01), Shimbo
patent: 4862234 (1989-08-01), Koden
patent: 4904056 (1990-02-01), Castleberry
patent: 4918504 (1990-04-01), Kato et al.
Tanaka Sakae
Watanabe Yoshiaki
Chadhuri Olik
Seikosha Co. Ltd.
Wilczewski M.
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