Method for producing a via hole to a doped region

Details Method for producing a via hole to a doped region Method for producing a via hole to a doped region

1993-04-27

2000-10-24

Trinh, Michael

Semiconductor device manufacturing: process

Chemical etching

Altering etchability of substrate region by compositional or...

438279, 438659, 438669, 438924, H01L 21302

Patent

active

061367176

ABSTRACT:
A method for producing a via hole to a doped region in a semiconductor device, including the steps of: producing the doped region in a substrate such that the doped region is limited by insulating regions at least at a surface of the substrate; depositing an undoped silicon layer surface-wide on the substrate; producing a doped region in the silicon layer that overlaps a region for the via hole; selectively removing the undoped silicon of the silicon layer relative to the doped region of the silicon layer; producing an insulating layer surface-wide; and forming the via hole in the insulating layer by selective anisotropic etching relative to the doped region of the silicon layer.

REFERENCES:
patent: 4090915 (1978-05-01), Keller
patent: 4231820 (1980-11-01), Henry
patent: 4438556 (1984-03-01), Komatsu et al.
patent: 4549914 (1985-10-01), Oh
patent: 4569123 (1986-02-01), Ishii et al.
patent: 4601778 (1986-07-01), Robb
patent: 4629520 (1986-12-01), Ueno et al.
patent: 4729969 (1988-03-01), Suda et al.
patent: 4748492 (1988-05-01), Iwase et al.
patent: 4868138 (1989-09-01), Chan et al.
patent: 4992389 (1991-02-01), Ogura et al.
patent: 5019527 (1991-05-01), Ohshima et al.
patent: 5081065 (1992-01-01), Jonkers et al.
Patent Abstracts of Japan, vol. 8, No. 41 (C-211) Feb. 22, 1984 and JP-a-58 199 869 (Matsushita Denki Denki Sangyo K.K.) Nov. 21, 1983.
"SDX: A Novel Self-Aligned Technique and Its Application to High-Speed Bipolar LSI's," Y. Yamamoto, et al., IEEE Transactions on Electron Devices Bd. 35, Nr. 10, Oct., 1987.
"A Self-Aligning Polysilicon Electrode Technology (SPEL) For Future LSTS," Y. Misawa, et al., International Electron Devices Meeting Dec. 6, 1987, Washington, D.C., pp. 32-35.
K. H. Kuesters, et al., "A High Density 4 bit dRAM Process Using a Fully Overlapping Bitline Contact (FoBiC) Trench Cell", Sympos. on VLSI Technology, 1987 Tech. Digest, pp. 93-94 ff.
K. H. Kuesters, et al., "A Self Aligned Contact Process With Improved Surface Planarization", ESSDERC 1988, Journal de Physique, pp. 503-506 ff.
K. Sasaki, "Silicided Source/Drain Process for MOSFET", IBM Technical Disclosure Bulletin, vol. 34, No. 3, Aug., 1991, pp. 42-43.
Bob Reuss, et al., "High Selectivity Contact Etch for BiCMOS and CMOS", Motorola, Inc., Technical Developments, vol. 14, Dec. 1991, pp. 97-98.

Affiliated with

Also associated with

Rating

Method for producing a via hole to a doped region does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for producing a via hole to a doped region, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for producing a via hole to a doped region will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1963563