Method for producing a transistor structure

Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Including isolation structure

Reexamination Certificate

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C438S202000, C438S234000, C438S309000, C438S338000, C438S353000, C257SE21350, C257SE21608, C257SE27046, C257SE27053, C257SE29034

Reexamination Certificate

active

07371650

ABSTRACT:
A method for fabricating a transistor structure with a first and a second bipolar transistor having different collector widths is presented. The method includes providing a semiconductor substrate, introducing a first buried layer of the first bipolar transistor and a second buried layer of the second bipolar transistor into the semiconductor substrate, and producing at least a first collector region having a first collector width on the first buried layer and a second collector region having a second collector width on the second buried layer. A first collector zone having a first thickness is produced on the second buried layer for production of the second collector width. A second collector zone having a second thickness is produced on the first collector zone. At least one insulation region is produced that isolates at least the collector regions from one another.

REFERENCES:
patent: 4379726 (1983-04-01), Kamamaru et al.
patent: 4882294 (1989-11-01), Christenson
patent: 2001/0045619 (2001-11-01), Dekker et al.
patent: 2002/0079554 (2002-06-01), Okawa et al.
patent: 26 33 569 (1976-07-01), None
patent: 100 44 838 (2000-09-01), None
patent: 1 480 050 (1977-07-01), None
patent: 7323812 (1973-07-01), None
patent: 58009354 (1983-01-01), None
patent: 58159346 (1983-09-01), None
patent: 62154779 (1987-07-01), None
patent: 2003174034 (2003-06-01), None
patent: WO 97/17726 (1997-05-01), None
Bipolar Transistor with Pedestal Subcollector Regions Self-Aligned Underneath Field Oxide Regions, pp. 252-253, 700 IBM Technical Disclosure Bulletin, vol. 31, No. 3, Aug. 1988.
M. Racanelli, K. Schuegraf, A. Kalburge, A. Kar-Ray, B. Shen, C. Hu, D. Chapek, D. Howard, D. Quon, F. Wang, G. U'ren, L. Lao, J. Zheng, J. Zhang, K. Bell, K. Yin, P. Joshi, S. Akhtar, S. Vo, T. Lee, W. Shi and P. Kempf,Ultra High Speed SiGe NPN for Advanced BiCMOS Technology, Silicon RF Platform Technologies, Conexant Systems, Inc.
International Search Report from corresponding PCT patent application No. PCT/DE03/03552.
Examination Report from corresponding PCT patent application No. PCT/DE03/03552.

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