Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
1998-06-11
2001-03-06
Fahmy, Wael (Department: 2822)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S221000, C438S427000
Reexamination Certificate
active
06197657
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a method for producing a semiconductor device. More particularly, it relates to a method for forming a shallow trench isolation (STI).
DISCUSSION ON THE RELATED ART
FIG. 6
illustrates an example of a conventional trench device isolation forming method, and is a cross-sectional view of a semiconductor substrate for schematically showing the production process step-by-step.
First, a silicon oxide film
17
is formed by thermal oxidation on a silicon substrate
16
to a film thickness of 300 Å (30 nm). On the silicon oxide film
17
, there is formed, as a stop film
18
for chemical mechanical polishing (CMP), a silicon nitride film, having a polishing rate by CMP lower than that of an insulating film used for device isolation (silicon oxide film), to a film thickness of 1000 Å (100 nm) by chemical vapor deposition (CVD).
The role of the initially formed silicon oxide film
17
is to relieve the stress between the silicon nitride film as the stop film
18
and the silicon substrate
16
.
Then, a mask
19
is selectively formed by a well-known photolithographic technique in an area which is later converted to a diffusion layer (active region).
Then, an area not covered by the mask
19
, that is the stop film
18
and the silicon oxide film
17
of the isolation regions, is removed by anisotropic etching. The silicon substrate
16
is also anisotropically etched to a depth of 3000 Å (300 nm) to form a trench
20
in the isolation region.
After forming the trench
20
, the mask
19
is removed and a silicon oxide film as an insulating film is formed on the entire surface of the semiconductor substrate to a film thickness of 4500 Å (450 nm) by CVD to fill the trench
20
.
Then, planarization is carried out by CMP until the stop film
18
on the diffusion layer (active region) is completely exposed, as shown in
FIG. 6
c
. After CMP, the stop film
18
has a film thickness is of the order of 600 Å (60 nm), having been slightly polished.
As a matter of course, the upper surface of the insulating film on the isolation regions is of substantially the same height as the upper surface of the stop film
18
.
Then, the stop film
18
is removed by etching, as shown in
FIG. 6
d
. For etching, wet etching by phosphoric acid, having a high etching selectivity of the stop film (nitride film) as compared to the silicon oxide film, is usually employed.
The result is that an insulating film
21
a
, protruded approximately 600 Å (60 nm) from the wafer surface, is produced in the isolation regions.
Then, the silicon oxide film
17
of a film thickness of 300 Å (30 nm) is wet-etched for removing the silicon oxide film. For this wet etching, a hydrofluoric acid or a hydrofluoric acid-containing liquid, affecting the underlayer to a lesser extent, is used.
Since the insulating film
21
a
also is a silicon oxide film, it is also etched at this time. However, the silicon oxide film by CVD is coarser than the silicon oxide film formed by thermal oxidation, with the etching rate by wet etching being typically faster by a factor of approximately three times by CVD than that by thermal oxidation.
Thus, there is formed a divot
22
with a radius of 300 Å (30 nm) around the insulating film
21
a
of the isolation regions to expose the sidewall of the trench
20
.
The process of formation of the divot (recess)
22
is explained with reference to
FIG. 7
, which is a cross-sectional view showing the rim of the trench device isolating area of
FIG. 6
d
to an enlarged scale.
If the silicon oxide film
17
with the film thickness of 300 Å (30 nm) by the thermal oxidation is wet-etched, the insulating film
21
a
, which is the silicon oxide film by CVD, is etched by approximately 900 Å (90 nm), so that the height of the upper surface is equal to that of the silicon substrate
16
.
However, since the wet etching is isotropic, it proceeds from a broken line
1
to a broken line
3
in
FIG. 7
, around the rim of the isolation regions, until the divot
22
is ultimately formed, as shown in
FIG. 6
e.
If a gate oxide film and a gate electrode are formed in this state for fabricating a transistor, there is formed unintentionally a transistor, on the trench sidewall of the diffusion layer (active region) and in particular at a corner where the electrical field is concentrated as discussed by Andres Bryant in a thesis (“Characteristics of CMOS Device Isolation for the ULSI Age” IDEM Tech. Dig., p. 671, 1994), thus producing adverse effects, known as humps or kinks, on inherent transistor characteristics.
There are also occasions where, in etching the gate electrode, the gate electrode material is left in the divot in the form of side walls due to sharp step difference by the divot to give rise to shorting across gate electrodes.
As discussed above, since a divot is produced around the isolation region with the conventional trench device isolation forming method, there is unintentionally formed a transistor in the trench sidewall of the diffusion layer (active region), in particular at a corner where the electrical field is concentrated, thus giving rise to adverse effects termed humps or kinks on the inherent transistor characteristics.
There are also occasions wherein, in gate etching, the gate electrode material is left in the divot in the form of sidewalls due to sharp step difference by the divot to give rise to shorting across gate electrodes.
In view of the above-described problems of the prior art, it is an object of the present invention to provide a method for producing a semiconductor device in which, in wet etching the silicon oxide film on the semiconductor substrate during formation of the shallow trench isolation (STI), the first insulating layer of the isolation region is prevented from being etched to produce a divot at the isolation end region to improve the yield, reliability and productivity of the semiconductor device.
Further objects of the present invention will become apparent in the entire disclosure.
For accomplishing the above object, the present invention generally resides in selectively forming an insulating film in a trench rim portion where a divot is likely to be produced for preventing the divot from being produced, or in forming a divot and subsequently selectively forming an insulating film in this divot for eliminating the divot prior to formation of the gate oxide film.
More specifically, one aspect of the present invention resides in a method for producing a semiconductor device including (a) forming a stop film for planarization over a semiconductor substrate, (b) removing the stop film of isolation regions by etching and further etching the semiconductor substrate to form a trench, (c) forming a first insulating film on the semiconductor substrate to fill the trench, (d) removing the first insulating film on the stop film by planarization, (c) removing the stop film, (f) forming a second insulating film after removing the stop film and before forming a gate oxide film and (g) etching the second insulating film.
According to the present invention, first and second insulating films are formed by chemical vapor deposition (CVD).
According to the present invention, planarization is achieved by chemical mechanical polishing (CMP).
According to the present invention, etching of the second insulating film is carried out by isotropic etching. Preferably, the etching is wet etching.
According to the present invention, the second insulating film is a silicon oxide film.
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Andres Bryant et al., “Characteristics of CMOS Device Isolation for the ULS
Fahmy Wael
NEC Corporation
Sughrue Mion Zinn Macpeak & Seas, PLLC
Vockrodt Jeff
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