Method for producing a roughened surface capacitor

Details Method for producing a roughened surface capacitor Method for producing a roughened surface capacitor

1992-12-21

1993-11-30

Kunemund, Robert

Fishing, trapping, and vermin destroying

437 60, 437919, H01L 2170, H01L 2700

Patent

active

052665143

ABSTRACT:
A new method to produce a microminiturized capacitor having a roughened surface electrode is achieved. The method involves depositing a first polycrystalline or amorphous silicon layer over a suitable insulating base. The silicon layer is either in situ heavily, uniformly doped or deposited undoped and thereafter heavily doped by ion implantation followed by heating. The structure is annealed at above about 875.degree. C. to render any amorphous silicon polycrystalline and to adjust the crystal grain size of the layer. The polysilicon surface is no subjected to a solution of phosphoric acid at a temperature of above about 140.degree. C. to partially etch the surface and cause the uniformly roughened surface. A capacitor dielectric layer is deposited thereover. The capacitor structure is completed by depositing a second thin polycrystalline silicon layer over the capacitor dielectric layer.

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patent: 5068199 (1991-11-01), Sandhu
patent: 5082797 (1992-01-01), Chan et al.
patent: 5110752 (1992-05-01), Lu
"A Capacitor-Over-Bit-Line (COB) Cell with a Hemispherical-Grain Storage Node for 64Mb DRAMs" by M. Sakao et al. IEDM 1990 Technical Digest pp. 655-658
"Rugged Surface Poly-Si Electrode and Low Temperature Deposited Silicon Nitride for 64 MBIT and Beyond STC DRAM Cell" by M. Yoshimaru et al, IEDM 1990 Technical Digest pp. 659-662.
"Electrical Characterization of Textured Interpoly Capacitors for Advanced Stacked DRAMs", by P. Fazan et al. IEDM 1990 Technical Digest, pp. 663-666.

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