Method for producing a package for a semiconductor device

Details Method for producing a package for a semiconductor device Method for producing a package for a semiconductor device

1986-02-11

1987-12-01

Weston, Caleb

Adhesive bonding and miscellaneous chemical manufacture

Methods

Surface bonding and/or assembly therefor

156250, 156252, 357 74, B32B 3114

Patent

active

047102500

ABSTRACT:
A package for a semiconductor device comprising three laminated ceramic sheets: a first sheet provided with a chip stage on the upper surface thereof, a second sheet provided with a first chip-inserting window for exposing the surface of the chip stage and provided with an internal conductor pattern formed at least on the upper surface thereof; and a third sheet provided with a second window for exposing the first chip-inserting window and for exposing a wire-bonding area located adjacent to the periphery of the first chip-inserting window, characterized in that marks for recognizing the location of the first chip-inserting window are essentially aligned, this alignment being effected in that the first chip-inserting window and marks for recognizing the location of the first chip-inserting window are simultaneously formed with the same mold, the marks for recognizing the location of the first chip-inserting window being formed in the wire-bonding area of the second green sheet.

REFERENCES:
patent: 3518756 (1970-07-01), Bennett et al.
patent: 3770529 (1973-11-01), Anderson
patent: 3778686 (1973-12-01), Galvin et al.
patent: 4007479 (1977-02-01), Kolwalski
patent: 4066485 (1978-01-01), Rosnowski et al.
patent: 4288841 (1981-09-01), Gogal
patent: 4505806 (1985-03-01), Yamada
C. R. Herring et al.: "Chip Carrier with Locating Indicia", Western Electric Technical Digest, Nr. 54, Apr. 1979, pp. 9-10.
Patents Abstracts of Japan, vol. 7, nr. 115 (E-176) (1260), May 19, 1983, European Serarch Report, 12-21-84, The Hague.

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