Fishing – trapping – and vermin destroying
Patent
1989-08-21
1991-12-03
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437194, 437195, 437913, H01L 21441
Patent
active
050700359
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a method for producing a compound semiconductor device, and more particularly to an effective technique adapted for producing compound semiconductor devices for example an InP semiconductor substrate on which a MES (Metal Semiconductor) type diode, a MIS (Metal Insulator Semiconductor) type diode, a MES type field effect transistor FET, or a MIS type field effect transistor is fabricated.
BACKGROUND TECHNIQUE
Compound semiconductors such as GaAs, InP and so on have been expected to be used as high speed devices because their electron mobility and saturation drift velocity are higher than Si (silicon). Already GaAs MESFET (Metal Semiconductor Field Effect Transistor) has been practically used.
Although superior properties were expected of InP, such superior properties in comparison with GaAs, InP have not been practically used for producing MESFET on account of high barrier height and difficulty in producing a Schottky junction with small reverse leakage current.
Conventionally, several attempts to interpose a thin insulating layer such as Al.sub.2 O.sub.3, SiO.sub.2 having a thickness of about 30 .ANG. between an InP and a gate electrode metal have been proposed in order to improve the barrier height of a Schottky diode made of InP.
However, such various attempts have provided only an InP Schottky diode with a barrier height .PHI. B of at its highest of 0.5 eV obtained from current-voltage characteristic, or large reverse leakage current. Further a conventional Schottky diode was possessed of poor properties such as an ideal factor n=1.5 to 2.0 representing completeness of the Schottky contact. The ideal factor n is deduced from the following equation representing the relationship between a forward current and voltage of the Schottky diode; ##EQU1## where, the saturation current Io is represented by following equation; ##EQU2## where, A represents the Richardson constant.
On the other hand, the general phenomena of semiconductor devices, the condition of the semiconductor surface remarkably influences characteristics of the semiconductor device. In a silicon semiconductor device, the density of interface trap density between Si and SiO.sub.2 layers is remarkably low and its insulating layer per se is stable so that good characteristics of a semiconductor device can be provided. However, a required insulating layer having a low interface trap density for a compound semiconductor has not yet been provided.
For example, various materials such as evaporated SiO and CVD-SiO.sub.2 (Chemical Vapor Deposition) have been studied for a long period of time in connection with use thereof as an insulating layer for the InP made MIS diode or MISFET. They do not possess a low interface trap density and a small current drift. In recent years, some attempts have been made to produce a special insulating layer (for example, AIPxOy) including the V-group elements by means of a thermal CVD method in order to control V-group elements.
In the insulating layer grown by using a hot CVD method, however, the surface of InP semiconductor should be exposed to high temperatures from 300.degree. to 450.degree. C. immediately prior to the formation of an insulating layer. This will possibly cause a decomposition of the InP semiconductor surface and vapor phosphorus thereby resulting in a problem for controlling the V-group elements. As a result, this method has not provided a desired insulating layer with an excellent interface property.
It is an object of the present invention to provide a method for producing an InP-made Schottky diode with a high barrier height and an excellent current-voltage characteristics.
Another object of the present invention is to provide a method for producing a semiconductor device including a III-V group (indium and/or phosphorus) compound semiconductor which ensures a decrease in the density of the state at the surface of the device, improves the capacitance-voltage characteristics of a MIS type diode, and provides a MISFET with a good performance.
DE
REFERENCES:
patent: 3438121 (1969-04-01), Wanlass et al.
patent: 4172158 (1979-10-01), Li
patent: 4731293 (1988-03-01), Ekholm et al.
patent: 4960718 (1990-10-01), Aina
T. Sawada, et al., "InP MISFET's with Al.sub.2 O.sub.3 /Native Oxide Double-Layer Gate Insulators", IEEE Trans. on Electron Devices, vol. ED. 31, #8, Aug. '84, pp. 1038-1043.
H. L. Chang, et al., "Preparation and Electrical Propeties of InP.sub.x O.sub.y Gate Insulators on InP", Appl. Phys. Lett. 48 (5), 3 Feb. 1986, pp. 375-377.
"InP High Mobility Enhancement MISFET's Using Anodically Grown Double-Layer Gate Insulator", #8093--Electronics Letters, vol. 18 (1982) #17, pp. 742-743.
P. O'Connor, T. P. Pearsall, K. Y. Cheng, A. Y. Cho, J. C. M. Hwang, K. Alavi, "In.sub.0.53 Ga.sub.0.47 As FET's with Insulator-Assisted Schottky Gates", IEEE Electron Device Letters, vol. EDL-3, No. 3 (Mar. '82) pp. 64-66.
Hattori Kazuo
Taniguchi Mitsuhiro
Fleck Linda J.
Hearn Brian E.
Nippon Mining Co., Ltd.
LandOfFree
Method for producing a III-V compound semiconductor device with does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for producing a III-V compound semiconductor device with , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for producing a III-V compound semiconductor device with will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1696822