Active solid-state devices (e.g. – transistors – solid-state diode – With specified dopant – Deep level dopant
Reexamination Certificate
2001-07-03
2002-10-22
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
With specified dopant
Deep level dopant
C257S655000, C257S656000, C438S543000
Reexamination Certificate
active
06469368
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of power electronics. It relates in particular to a method for producing a high-speed power diode with soft recovery, and to a power diode.
2. Background Information
Particularly with low bias currents and high voltages, an abrupt breakdown in the reverse current, which is referred to as a “snap off”, occurs during the commutation, without any circuitry, of high-speed, optimized-loss and optimized-reliability diodes (that is to say a diode having a semiconductor substrate which is distinguished by the silicon being thin and by a high basic material resistance).
As described in a number of places, such a “snap-off” or such a hard switching response can be shifted by various measures toward higher voltages, which are above the voltages that occur during operation. This is achieved by an axial profile of the carrier life in the component, which is produced, for example, by diffusion of heavy-metal atoms or by ion bombardment (He++ or H+).
For example, U.S. Pat. No. 4,140,560 has proposed that a gold concentration with a pronounced concentration gradient be produced in the substrate, leading to soft recovery, by diffusion of gold atoms into the semiconductor substrate of a high-speed diode.
The “snap-off” is also assisted by a short effective charge carrier life, as is required for large-area diodes designed for low dynamic losses. Reducing the switch-off losses by increasing the ion dose in the case of diodes which are bombarded purely by ions is also limited by the high reverse current in the component which results in consequence.
In consequence, neither combined bombardment with ions and electrons nor increase in the ion dose achieves the aim.
According to another known proposal (DE-A1-41 35 258) the semiconductor substrate of a high-speed power diode is subdivided by specific partial treatment (for example bombardment with protons or helium nuclei and electron bombardment) into two separate area elements located alongside one another. The partial diodes formed in this way differ in that one partial diode has soft recovery while the other has a hard “snap off” response. The desired overall diode response is obtained by connecting the two diode elements in parallel.
It has also been proposed (DE-A1-196 09 244) for the two abovementioned diode elements to be designed in such a way that regions are arranged distributed in an area of the semiconductor substrate which is not subjected to bombardment or is subjected to basic bombardment with electrons, in which regions bombardment or additional bombardment has been carried out. A mask in the form of strips is used, for example, to produce the distributed regions. This results in the carrier life having a lateral profile in addition to the axial profile. The combination of the two profiles then leads to the desired diode switching response.
The high-speed power diodes produced using the known methods and with soft recovery admittedly have a better switching response, but have undesirably high reverse currents and reverse losses.
SUMMARY OF THE INVENTION
The object of the invention is thus to specify a method for producing a high-speed power diode with soft recovery, which leads to components with low reverse losses, and to specify a power diode produced using this method.
The object is achieved by the totality of the features of claims 1 and 8. The essence of the invention is that, after ion bombardment over the entire surface, the component is masked during the subsequent electron bombardment to produce a three-dimensional life distribution. In principle, this results in two diode sub-areas, which can be regarded as parallel-connected diodes with different dynamic and steady-state characteristics. The diode part with a high bombardment dose (ion bombardment+electron bombardment) has a very high conduction resistance and carries virtually no forward current. Accordingly, its proportion of the total storage charge of the diode is low. The other sub-area (the part not subject to electron bombardment) carries virtually the entire forward current and governs the “recovery charge” and recovery response.
Since this greatly reduces the active area, it results in increased current densities with a relatively long carrier life, which leads to correspondingly soft snap-off response. The bombardment with electrons leads to the increase in the reverse current being less than that for pure ion bombardment for a comparable forward voltage drop, so that the reverse losses also remain low. The reduced active area also means that there are sub-areas of the diode which, owing to the additional bombardment, carry no forward current, or only a reduced forward current, and thus produce no switching losses, or only small switching losses, when the diode is being switched off. Thus, overall, the area in which switch-off losses are generated becomes smaller. The heat losses which are produced are, however, dissipated outward distributed over the entire substrate area, as before. This results in a reduction in the thermal resistance R
th
being achieved, related to the active area of the diode.
A first preferred refinement of the method according to the invention is distinguished in that a perforated plate, preferably composed of steel or molybdenum, is used for the second, masked bombardment. Such a mask allows the regions of the two diode elements to be distributed optimally.
Further profiling in the lateral direction can be achieved if, according to a second preferred refinement to the invention, a gauze, preferably composed of steel wire, is used for the second, masked bombardment. With an electron acceleration energy of, for example, 2.5 MeV, such a gauze with a wire thickness of 1 mm leads to total shielding at the node points and to partial shielding in the areas which are covered once, which leads to a limited electron penetration depth into the silicon, and thus to an additional defect profile. The bombardment takes place with its full energy in the areas which are not covered, which results in the production of an axially constant defect distribution.
The surface area which is not covered by the mask is preferably between 20% and 80%, preferably approximately 50%, of the total area of the mask.
REFERENCES:
patent: 4140560 (1979-02-01), Rodov
patent: 4281336 (1981-07-01), Sommer et al.
patent: 5747872 (1998-05-01), Lutz et al.
patent: 6351024 (2002-02-01), Ruff et al.
patent: 4135258 (1993-04-01), None
patent: 4337329 (1995-05-01), None
patent: 19609244 (1997-09-01), None
patent: 0878849 (1998-11-01), None
patent: 08102545 (1996-04-01), None
ABB (Schweiz) AG
Burns Doane Swecker & Mathis L.L.P.
Ho Tu-Tu
Nelms David
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