Fishing – trapping – and vermin destroying
Patent
1995-06-01
1997-02-04
Tsai, H. Jey
Fishing, trapping, and vermin destroying
437984, 437983, H01L 218247
Patent
active
055997279
ABSTRACT:
According to the present invention, a method for producing a nonvolatile semiconductor memory device is provided. The method includes the steps of: forming stripe-shaped silicon portions including a plurality of first portions to be used as a plurality of floating gates and a plurality of second portions interposed between two adjacent portions of the plurality of first portions by patterning a silicon film; forming a conductive film so as to cover an insulating film; forming a control gate so as to cover the plurality of first portions of the stripe-shaped silicon portions by patterning the conductive film; converting the plurality of second portions of the stripe-shaped silicon portions into a silicon oxide film, and forming the plurality of floating gates from the plurality of first portions by thermally oxidizing the plurality of second portions; and implanting impurity ions through the silicon oxide film into the active region on the semiconductor substrate by using the control gate as a mask, thereby forming a source region and a drain region in the active region.
REFERENCES:
patent: 5029130 (1991-07-01), Yeh
patent: 5045488 (1991-09-01), Yeh
patent: 5067108 (1991-11-01), Jenq
Salsbury et al, "High Performance MOS EPROMs Using a Stacked-Gate Cell", 1977 IEEE International Solid-State Circuits Conference, pp. 186-187, 1977.
Perlegos et al, "A 64K EPROM Using Scaled MOS Technology", 1980 IEEE International Solid-State Circuits Conference, pp. 142-143, p. 269, 1980.
Van Buskirk et al, "A 200ns 256K HMOSII EPROM", 1983 IEEE International Solid-State Circuits Conference, pp. 162-163, p. 301, 1983.
Gupta et al, "A 5V-Only 16K EEPROM Utilizing Oxynitride Dielectrics and EPROM Redundancy", 1982 IEEE International Solid-State Circuits Conference, pp. 184-185, p. 317, 1982.
Kynett et al, "An In-System Reprogrammable 256K CMOS Flash Memory", 1988 IEEE International Solid-State Circuits Conference, pp. 132-133, p. 330, 1988.
Tam et al, "A High Density CMOS 1-T Electrically Erasable Non-Volatile (Flash) Memory Technology", 1988 Symposium on VLSI Technology--Digest of Technical Papers, pp. 31-32.
Woo et al, "A Poly-Buffered Face Technology For High Density Flash Memories", 1991 Symposium on VLSI Technology--Digest of Technical Papers, pp. 73-74.
Sato et al, "An Ultra-Thin Fully Depleted Floating Gate Technology For 64Mb Flash and Beyond", 1994 Symposium on VLSI Technology--Digest of Technical Papers, p. 65.
Wolf et al., Silicon Processing for the VLSI ORA, vol I Process technology, p. 175, Laftso Press 1986.
Hakozaki Kenji
Sato Shin'ichi
Sharp Kabushiki Kaisha
Tsai H. Jey
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