Method for producing a flip chip package

Details Method for producing a flip chip package Method for producing a flip chip package

2001-03-22

2002-04-02

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

C438S612000, C438S974000

Reexamination Certificate

active

06365435

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to producing a flip chip semiconductor package and more particularly to a method of applying underfill when producing such a package.
BACKGROUND OF THE INVENTION
Flip chip semiconductor packages are known. A flip chip package comprises a semiconductor chip or die which has a pattern of pads on one surface; a substrate with a corresponding pattern of conductors on a first surface, and a second surface, opposite the first surface, with a pattern of external conductors; interconnects that couple the pads to the conductive locations; and underfill that fills the gap between the die and the substrate.
A first, and relatively well known, method of forming the flip chip package is to raise or bump the pads on the semiconductor die, then flip the chip over and place it with the bumps on the pattern of conductors. When the bumps are deposits or layers of solder, or solder balls, the assembly is heated and the solder between the pads and conductors melts to form an interconnect between a pad and a corresponding conductor.
Typically, the underfill is an epoxy based liquid whose viscosity will significantly decrease with raising temperature. The underfill is applied at the edges of the flipped die, and through capillary action the underfill is drawn in and flows into the gap. The process of filling the gap with underfill presents a variety of difficulties, most of which relate to the incomplete filling of the gap with the underfill.
A second method of forming a flip chip package attempts to shorten the process flow and in particular overcome the problem of applying underfill by using so called, no-flow underfill. With this method, the no-flow underfill is applied to the first surface of the substrate before the bumped surface of the die is placed on the substrate. This method substantially addresses the problems and difficulties associated with incomplete filling of the gap between the substrate and the die encountered using the first method.
However, it has been found that this method results in air bubbles being trapped in the no-flow underfill. Air bubbles cause voids in the completed flip chip semiconductor packages, and voids, as with the first method, affects the reliability and cosmetics of the flip chip semiconductor package.
In industry, customers of such packages specify a tolerable void criterion in a package in terms of the size of voids and the distribution of the voids. Packages with a void count and distribution which exceeds the specified criteria are rejected. A known criteria is, no bump can be totally isolated from underfill. In other words, a bump should not have a void surround it. Hence, there is a need to control the void formation in flip chip semiconductor packages in order to meet the void criteria and produce more reliable packages.
BRIEF SUMMARY OF THE INVENTION
The present invention seeks to provide a method for producing a flip chip semiconductor package, which overcomes or at least reduces the abovementioned problems of the prior art.
Accordingly, in one aspect, the present invention provides a method for forming a flip-chip semiconductor package, the method comprising the steps of:
a) providing:
i) a semiconductor die having a plurality of pads thereon, wherein the pads are arranged in a pattern, and wherein at least some of the plurality pads has at least one conductive bump thereon;
ii) a substrate having a plurality of conductive locations thereon, wherein at least some of the plurality of conductive locations are arranged in a corresponding pattern, the at least some of the plurality of conductive locations for receiving at least some of the bumps; and
iii) underfill;
b) heating the substrate to an elevated temperature relative to the temperature of the underfill while dispensing the underfill on the substrate; and
c) placing the semiconductor die on the substrate with the underfill therebetween, wherein the at least some of the plurality of pads are substantially aligned with the at least some of the plurality of conductive locations.
In another aspect the present invention provides a method for forming a flip-chip semiconductor package, the method comprising the steps of:
a) providing:
i) a semiconductor die having a plurality of pads thereon, wherein at least some of the plurality of pads are arranged in a pattern;
ii) a bumped substrate having a plurality of conductive locations thereon, wherein at least some of the plurality of conductive locations are arranged in a corresponding pattern, and wherein at least some of the plurality of conductive locations has at least one conductive bump thereon, the at least some of the plurality of conductive locations for coupling to at least some of the plurality of pads; and
iii) underfill;
b) heating the bumped substrate to an elevated temperature relative to the temperature of the underfill while dispensing the underfill on the bumped substrate; and
c) placing the semiconductor die on the bumped substrate with the underfill therebetween, wherein the at least some of the plurality of pads are substantially aligned with the at least some conductive locations.


REFERENCES:
patent: 5795818 (1998-08-01), Marrs
patent: 6133066 (2000-10-01), Murakami
patent: 6163463 (2000-12-01), Marrs

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