Metal working – Electric condenser making – Solid dielectric type
Reexamination Certificate
1998-02-11
2001-07-10
Young, Lee (Department: 3729)
Metal working
Electric condenser making
Solid dielectric type
C029S025410, C174S050540, C174S250000, C174S255000, C174S260000, C439S068000, C361S301100, C361S301200, C361S306300, C361S313000, C361S314000, C361S315000, C361S320000, C361S328000, C361S763000, C361S766000, C361S821000
Reexamination Certificate
active
06256850
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a printed circuit board with embedded decoupling capacitance and method for producing same. More particularly, the invention relates to printed circuit boards having very high integrated decoupling capacitances which are created by multi-layering pre-drilled or pre-etched conductor foils that have been coated with a dielectric material. The pre-drilled or pre-etched conductor foils are in the form of either voltage or ground planes. After coating with a dielectric material, the foils are stacked up such that voltage and ground planes alternate. The alternating stack then is laminated together with other signal planes to form the desired multi-layer circuit board.
BACKGROUND OF THE INVENTION
Electronic circuits contain many (sometimes millions) of components such as resistors, capacitors, inductors, diodes, electro-mechanical switches, and transistors. High density packaging of electronic components is particularly important to allow fast access to large amounts of data in computers. High density electronic circuit packages also are important in high frequency devices and communications devices. The components are connected to form circuits and circuits are connected to form functioning devices. The connections perform power and signal distribution. In a multi-layer electronic circuit package, some layers of the package serve as power planes and other layers serve as signal planes, depending on the operational requirements of the device. The devices require mechanical support and structural protection. The circuits themselves require electrical energy to function. The functioning devices, however, produce heat, or thermal energy which must be dissipated so that the devices do not stop functioning. Moreover, while high density packaging of a number of components can improve performance of the device, the heat produced by the power-consuming components can be such that performance and reliability of the devices is adversely impacted. The adverse impact arises from electrical problems such as increased resistivity and mechanical problems such as thermal stress caused by increased heat.
High density packages necessarily involve increased wiring density and thinner dielectric coatings between layers in a multi-layer electronic circuit package. The layers in a multi-layer package are electrically connected by vias and through-holes. The term “via” is used for a conductive pathway between adjacent layers in a multi-layer electronic circuit package. The term “through-hole” is used for a conductive pathway that extends to a non-adjacent layer. For high density packages the through-holes are increasingly narrow in diameter and the through-holes in each layer must be aligned precisely.
Electronic circuit packages, such as chips, modules, circuit cards, circuit boards, and combinations of these, thus must meet a number of requirements for optimum performance. The package must be structurally sturdy enough to support and protect the components and the wiring. In addition, the package must be capable of dissipating heat and must have a coefficient of thermal expansion that is compatible with that of the components. Finally, to be commercially useful, the package should be inexpensive to produce and easy to manufacture.
Electronic circuit packages, while used in both digital and analog circuits, find their greatest application in digital circuits. In digital circuits a narrow band around one discrete value of voltage corresponds to a logical “0” and another narrow band around a second discrete value of voltage corresponds to a logical “1”. Signals having these properties are “digital signals.” Digital information processing depends upon the transmission, storage and application of these digital signals.
In digital information processing, a signal changes from one binary level to another. This change is ideally transmitted as a “step function.” However, this ideal step function becomes distorted because of resistance, capacitance, inductance, and transmission line effects in the transmission line and in other transmission lines in the package. Moreover, this step function, whether ideal or distorted, gives rise to still other distortions and spurious signals, i.e., noise, and induced signals on other lines in the circuit package. Thus, it is necessary to filter noise out of digital circuits.
Filtering may be accomplished in digital circuit packages by providing internal RC filter circuits of appropriate RC time constant and band pass characteristics, and thereby capacitively coupling, or decoupling, signal lines with, for example, power lines, ground lines, or other signal lines.
Attempts at providing embedded decoupling capacitance are known in the art. For example, in U.S. Pat. No. 5,027,253 to Lauffer, et al, an integral buried capacitor is provided comprising a first electrode connected by a wire to a first signal core and a second electrode connected by a wire to a second signal core. The second electrode at least partially overlaps the first electrode but is separated from it by a thin film of dielectric material. The two electrodes and the thin film of dielectric material define the integral buried capacitor.
In U.S. Pat. No. 5,261,153, to Lucas (“Lucas”), a method is provided for forming a capacitor element internally within a printed circuit board. Lucas discloses arranging uncured dielectric sheets with conductive foils laminated to either side and incorporated as a layer in a printed circuit board.
The method of Lucas requires that clearance holes in the conductive foils be defined by etching through a patterned photoresist material on each foil individually. The present invention allows a multitude of foils to be stacked together and drilled or punched simultaneously, hence creating a lower cost package. Additionally, the Lucas method is subject to reliability problems of plane to plane shorting due to dendritic copper plating along the glass fibers of the thin dielectric material. The non-glass dielectric of the present invention does not contain any defined dendritic copper paths.
SUMMARY OF THE INVENTION
It is an object of this invention to provide a printed circuit board with decoupled ground and power busses to provide proper switching stimulus.
A further object of this invention is to provide printed circuit boards with very high decoupling capacitance values.
A third object of this invention is to provide methods of fabrication of printed circuit boards with integrated decoupling capacitance.
Accordingly, a method is provided for producing a capacitor to be embedded in an electronic circuit package comprising the steps of selecting a first conductor foil, selecting a dielectric material, coating the dielectric material on at least one side of the first conductor foil, and layering the coated foil with a second conductor foil on top of the coating of dielectric material. Also claimed is an electronic circuit package incorporating at least one embedded capacitor manufactured in accordance with the present invention.
It is an advantage of the present invention that the capacitor provided is embedded into the electronic circuit package, reducing or eliminating the need for surface-mount capacitors.
It is a further advantage that the embedded capacitors provided decouple the ground and power busses to provide proper switching stimulus.
It is a further advantage that using the embedded capacitors provided results in printed circuit boards with very high decoupling capacitance values.
Other features and advantages of the present invention will become apparent in the following detailed description of the preferred embodiment of the invention taken in conjunction with the accompanying drawings and examples.
REFERENCES:
patent: 3635759 (1972-01-01), Howatt
patent: 4035768 (1977-07-01), Boldridge, Jr. et al.
patent: 4241378 (1980-12-01), Dorrian
patent: 4775573 (1988-10-01), Turek
patent: 4835656 (1989-05-01), Kitahara et al.
patent: 4864465 (1989-09-01), Robibins
patent: 4868711 (1989-09-01), Hirama et al.
patent: 50
Lauffer John M.
Papathomas Konstantinos
Chang Rick Kiltae
Hogg William N.
International Business Machines - Corporation
Young Lee
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