Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive...
Reexamination Certificate
2003-01-21
2004-11-23
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
C438S386000, C438S425000
Reexamination Certificate
active
06821863
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention lies in the semiconductor technology field. More specifically, the invention relates to a method for producing a cavity in a silicon substrate, such as a monocrystalline silicon substrate, wherein a cavity is incorporated in the silicon substrate and the wall of the cavity is covered by a covering layer at least in an upper end area. The invention also pertains to a semiconductor component having a cavity in a monocrystalline silicon substrate, which is covered by an epitaxial layer.
Semiconductor components such as DRAM memories are produced by a large number of technological method steps. In this case, it may be necessary to incorporate a cavity in a silicon substrate and then to fill the cavity for example with a layer sequence, in order to produce a trench capacitor. The trench capacitor is then conductively connected to a selection transistor in further production methods, with the selection transistor likewise being produced on the silicon substrate. This results in a memory cell for DRAM memory.
However, in other application areas (for example for microsystem technology) it is also necessary to incorporate cavities in a silicon substrate and to close the cavity. By way of example, pressure sensors are constructed in the form of cavities and are covered by a pressure membrane. The covered cavities represent either only an intermediate stage or a final stage in the production of a semiconductor component.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for producing a cavity in a monocrystalline silicon substrate and a semiconductor component having a cavity in a monocrystalline silicon substrate with an epitaxial covering layer, which overrcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which provides a simple method for producing a cavity in a silicon substrate and, furthermore, provides a semiconductor component having a cavity, with the cavity being covered by a covering layer which can be produced in a simple manner.
With the foregoing and other objects in view there is provided, in accordance with the invention, a production method for forming a covered cavity in a semiconductor substrate. The method comprises the following steps:
providing a monocrystalline silicon substrate having a silicon surface;
forming a cavity in the silicon substrate and covering walls of the cavity with a cover layer at least in an upper end region of the cavity;
depositing a covering layer on the silicon substrate with a selective epitaxial process; and
thereby growing the covering layer substantially only on the silicon surface to cover the cavity with the covering layer and to form a covered cavity in the monocrystalline silicon substrate.
One advantage of the novel method is that a cavity which is incorporated into a silicon substrate is covered with an epitaxial covering layer using a simple method. To do this, a cover layer is applied to the wall of the cavity, and a covering layer is then applied to the substrate using a selective epitaxial deposition method. The method for producing the covering layer is chosen in such a way that the material to be deposited does not grow on the cover layer. The opening (which is arranged on the surface of the substrate) of the cavity is thus covered completely by the selective epitaxial deposition method. A cavity with an epitaxial covering layer is thus produced in a monocrystalline silicon substrate in one simple production process. In particular, the monocrystalline structure in this case also remains in the covering layer, so that transistors can be produced on the covering layer.
In accordance with another feature of the invention, the cover layer is spaced from the surface of the silicon substrate by a predetermined width.
In accordance with an added feature of the invention, a silicon dioxide layer is applied as the cover layer. The use of a silicon dioxide layer offers a simple and reliable technology for application of a cover layer, on which a silicon layer which is deposited using a selective epitaxial deposition method does not grow.
In accordance with an additional feature of the invention, the cavity is filled with a stop layer once the covering layer has been applied. The stop layer is formed in such a way that the stop layer is not removed by a selective wet-etching method. This allows a selective wet-etching method to be used in order to remove the cover layer in the upper edge area of the wall. This results in a further preferred embodiment for a simple production method.
A light-sensitive lacquer, a photoresist, is preferably used as the stop layer whose cost is low and which can easily be introduced into the cavity, and can be removed from the trench once again, preferably by way of a plasma etching process.
In accordance with a preferred embodiment of the invention, the novel method is used to introduce a trench for a trench capacitor into a silicon substrate, but with the trench being at least partially filled with a dielectric layer and an electrically conductive layer only after high-temperature steps have been carried out, and hence producing a trench capacitor. The trench capacitor is itself incorporated in the silicon substrate, in the form of a cavity with an epitaxial covering layer, before the high-temperature steps are carried out. It is thus possible to use materials for the production of the trench capacitor which do not withstand the high-temperature processes (as are normally used for the production of a memory module) without damage, but which have preferred characteristics for the operation of the trench capacitor.
It is preferably possible to use dielectric materials which have a high dielectric constant but are not stable at temperatures of more than 800° C. Furthermore, metallic layers can be used as electrical electrodes or conductors for making contact with the trench capacitor. Incorporation of the metallic layers after carrying out the high-temperature processes offers the advantage that the metallic layers are not subject to the high temperatures, which therefore do not adversely affect the electrical operation of the trench capacitor or of the silicon substrate.
Experiments have shown that, when the covering layer is formed in accordance with the described method, the covering layer grows into the cavity to a predetermined depth. This improves the stability of the covering layer. The covering layer is thus less sensitive to mechanical damage.
With the above and other objects in view there is also provided, in accordance with the invention, a semiconductor component, comprising:
a monocrystalline silicon substrate having a cavity with a wall formed therein;
a cover layer (e.g., silicon dioxide) covering the wall of the cavity at least in an upper edge area thereof; and
an epitaxial layer (e.g., silicon) covering said cavity, said epitaxial layer projecting to a predetermined depth into said cavity, i.e., bulging into the cavity.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for producing a cavity in a monocrystalline silicon substrate and a semiconductor component having a cavity in a monocrystalline silicon substrate with an epitaxial covering layer, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
REFERENCES:
patent: 6156606 (2000-12-01), Michaelis
patent: 6200873 (2001-03-01), Schrems et al.
patent: 6258692 (2001-07-01), Chu et al.
pate
Pomplun Kerstin
Popp Martin
Schilling Uwe
Schupke Kristin
Temmler Dietmar
Greenberg Laurence A.
Infineon - Technologies AG
Mayback Gregory L.
Nguyen Dao H.
Stemer Werner H.
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