Semiconductor device manufacturing: process – Gettering of substrate – By implanting or irradiating
Reexamination Certificate
2001-10-01
2003-03-11
Chaudhuri, Olik (Department: 2813)
Semiconductor device manufacturing: process
Gettering of substrate
By implanting or irradiating
C438S476000
Reexamination Certificate
active
06531378
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a method for processing a monocrystalline Si-semiconductor wafer. The monocrystalline Si-semiconductor wafer has a front side which is at least partially processed with respect to a sequence of layer deposition processes.
Conventional microelectronic memory elements (DRAMs) mostly use oxide or nitride layers which have a dielectric constant of a maximum of about 8 as a storage dielectric. In order to make a storage capacitor smaller and to produce nonvolatile memories (FRAMs), “new type” capacitor materials (dielectrics or ferroelectrics) having distinctly high dielectric constants are needed. For that purpose, capacitor materials Pb(Zr,Ti)O
3
[PZT], SrBi
2
Ta
2
O
9
[SBT], SrTiO
3
[ST] and (Ba,Sr)TiO
3
[BST] are known from pages 51-53 of a generic publication entitled “Neue Dielektrika für Gbit-Speicherchips” [New Dielectrics for Gbit memory chips] by W. Hönlein, Phys. Bl. 55 (1999).
The use of those new type dielectrics/ferroelectrics with high epsilon presents problems for various reasons. For one thing, those new type materials can no longer be combined with the traditional electrode material (poly)silicon. For that reason, inert electrode materials such as, for example, Pt or conductive oxides (e.g. RuO
2
) must be used. Furthermore, a diffusion barrier (e.g. of TiN, TaN, Ir, IrO
2
and MoSi
2
) must be inserted between the electrode material and the conductive connecting structure (plug) to the transistor.
Finally, the production of such structures requires a position of the new type high-epsilon dielectrics/ferroelectrics in an oxygen atmosphere and the usually multiple tempering of the already partially processed Si-semiconductor wafer at temperatures above 550° C.
In practice, having to use those new type substances (metal and rare earth metals) for the high-epsilon dielectric/ferroelectric, the electrodes and the barrier layer, in connection with the requirements of having to use high process temperatures which favor diffusion processes, results in a considerably increased risk of contamination of the Si-semiconductor wafer during production.
U.S. Pat. No. 5,679,405 describes a method in which an Ar gas flow is conducted over the back of a semiconductor wafer which is mounted on a substrate holder in a CVD reactor in order to reduce adsorption of contamination.
U.S. Pat. No. 5,424,224 describes a method in which the back of a semiconductor wafer is protected by application of a protective SiO
2
or Si
3
N
4
layer during polishing of the front and of the edge of the wafer. The protective layer is removed again after the polishing process.
Patent Abstracts of Japan Publication No. 56-83948 describes a method for processing a semiconductor substrate in which a layer containing contamination and being formed of a semiconductor material or its oxide is applied to the back of the semiconductor substrate. The contamination is distributed in the semiconductor substrate in a later tempering step.
U.S. Pat. No. 4,053,335 describes a method for processing a monocrystalline Si-semiconductor wafer in which the semiconductor wafer is subjected to a temperature treatment step at a temperature of over 550° C. during the processing. Before the processing, a polycrystalline silicon layer is applied as a getter layer to the back of the Si-semiconductor wafer. A protective layer protecting against the penetration of contamination during the temperature treatment step, for example a silicon nitride layer, is applied to the polycrystalline silicon layer.
Similarly, in Patent Abstracts of Japan Publication No. 54-069964, silicon nitride layers are directly applied as protective layers to the front and back of a semiconductor substrate through the use of a plasma CVD process. The subsequent heat treatment step takes place at a temperature of about 500° C. and is used for reducing contact resistances of applied electrode layers.
U.S. Pat. No. 5,716,875 describes a method for producing CMOS transistors and ferroelectric capacitors on a semiconductor substrate in which silicon nitride layers are applied as protective layers to the side walls of the wafer and the back of the wafer substrate. As described therein, a LPCVD process can preferably be performed for the deposition.
In U.S. Pat. No. 5,223,734, a production method for semiconductor components is described in which the back of a semiconductor wafer is thinned and roughened by chemical/mechanical planarization (CMP). In that process, crystal dislocations are produced in the vicinity of the surface of the back of the wafer which are used as traps for moving contamination. That creates a getter layer through the use of which contamination in the semiconductor substrate can be trapped in a heat treatment step.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for processing a Si-semiconductor wafer which overcomes the hereinafore-mentioned disadvantages of the heretofore-known methods of this general type, which enables risks of contamination of the semiconductor wafer to be reduced during a tempering step and in which the Si-semiconductor wafer is at least partially processed at the front and is protected against contamination in a subsequent tempering step.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for processing a monocrystalline Si-semiconductor wafer, which comprises subjecting the Si-semiconductor wafer to a plurality of tempering steps at a temperature of over 550° C. A protective layer is applied to the back of the Si-semiconductor wafer, at least once before a tempering step. The protective layer protects against penetration of at least one metal and/or rare earth metal substance into the Si-semiconductor wafer during the tempering step. The protective layer is at least partially removed for removing a contaminated surface area between two of the tempering steps. Applying the protection layer to the back of the Si-semiconductor wafer in accordance with the invention prevents metal and/or rare earth metal substances from being able to become adsorbed at the “naked” back of the semiconductor wafer before or during the tempering step, from being able to pass into the monocrystalline Si material by diffusion and from contaminating it during the tempering step. Such contamination of the semiconductor material is unwanted since it can lead to an impairment of the life and/or electrical characteristics of the components which are produced on the front of the semiconductor wafer.
In accordance with another mode of the invention, the protective layer is a Si
3
N
4
barrier layer. It has been found that a nitride layer forms a decidedly efficient diffusion barrier, especially compared with Pt.
In accordance with a further mode of the invention, the Si
3
N
4
barrier layer is preferably deposited through the use of an LPCVD (Low Pressure Chemical Vapor Deposition) process. This provides a very “dense” nitride with a low etching rate and good diffusion barrier characteristics.
In accordance with an added mode of the invention, a SiO
2
buffer layer is suitably applied to the Si-semiconductor wafer before the Si
3
N
4
barrier layer is deposited. This prevents excessive tensions which can impair the homogeneity, the mechanical stability and the diffusion barrier effect of the Si
3
N
4
barrier layer, from building up between the monocrystalline silicon substrate and the Si
3
N
4
barrier layer.
In accordance with an additional mode of the invention, in a second preferred embodiment, the protective layer is a SiO
2
barrier layer. The SiO
2
barrier layer also counteracts contamination of the monocrystalline Si-semiconductor substrate, assuming that its effect is based on inclusion or enhancement processes of the substance or substances to be kept away in the layer to a greater extent than in the case of the Si
3
N
4
barrier layer.
In accordance with yet another mode of the invention, in a third preferred embodim
Chaudhuri Olik
Greenberg Laurence A.
Infineon - Technologies AG
Mayback Gregory L.
Smoot Stephen W.
LandOfFree
Method for processing wafer by applying layer to protect the... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for processing wafer by applying layer to protect the..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for processing wafer by applying layer to protect the... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3035157