Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having air-gap dielectric
Reexamination Certificate
2007-12-05
2010-06-22
Jackson, Jr., Jerome (Department: 2815)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Having air-gap dielectric
C438S422000, C257SE21319
Reexamination Certificate
active
07741191
ABSTRACT:
Densely spaced gates of field effect transistors usually lead to voids in a contact interlayer dielectric. If such a void is opened by a contact via and filled with conductive material, an electrical short between neighboring contact regions of neighboring transistors may occur. By forming a recess between two neighboring contact regions, the void forms at a lower level. Thus, opening of the void by contact vias is prevented.
REFERENCES:
patent: 4945070 (1990-07-01), Hsu
patent: 5789314 (1998-08-01), Yen et al.
patent: 6740549 (2004-05-01), Chen et al.
patent: 2002/0001936 (2002-01-01), Terauchi et al.
patent: 2002/0014679 (2002-02-01), Lee et al.
patent: 2002/0036349 (2002-03-01), Saito et al.
patent: 2004/0094821 (2004-05-01), Lur et al.
patent: EP 0 736 896 (1996-10-01), None
Foreign associate transmittal letter dated Jan. 24, 2008.
Translation of Official Communication issued Dec. 18, 2007.
Feustel Frank
Frohberg Kai
Mueller Sven
Budd Paul A
GlobalFoundries Inc.
Jackson, Jr. Jerome
Williams Morgan & Amerson
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