Method for preventing multi-level cache system deadlock in a mul

Details Method for preventing multi-level cache system deadlock in a mul Method for preventing multi-level cache system deadlock in a mul

1996-08-14

1997-05-20

Chan, Eddie P.

395448, 395449, 395469, 395490, 395496, G06F 1214

Patent

active

056320256

ABSTRACT:
A method for preventing deadlock due to the need for data exclusivity when performing forced atomic instructions in a multi-level cache in a multi-processor system. The system determines whether an aligned multi-byte word in which the data of a forced atomic instruction, such as an integer store operation, is exclusive in a first level cache. If so, the forced atomic instruction is allowed to enter a second level cache pipeline. If not, the forced atomic instruction is prevented from entering the second level cache pipeline and a cache miss and fill operation is initiated to cause the aligned word to be exclusive in the first level cache.

REFERENCES:
patent: 5058006 (1991-10-01), Durdam et al.
patent: 5136700 (1992-08-01), Thacker
patent: 5241641 (1993-08-01), Iwasa et al.
patent: 5287484 (1994-02-01), Nishii et la.
patent: 5406504 (1995-04-01), Denisco et al.

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