Method for preventing localized Cu corrosion during CMP

Details Method for preventing localized Cu corrosion during CMP Method for preventing localized Cu corrosion during CMP

2002-04-25

2004-04-27

Rose, Robert A. (Department: 3723)

Abrading

Abrading process

Utilizing fluent abradant

C451S057000

Reexamination Certificate

active

06726535

ABSTRACT:

FIELD OF THE INVENTION
This invention generally relates to chemical mechanical polishing (CMP) and more particularly to a method for preventing localized copper (Cu) anodic corrosion in a chemical mechanical polishing (CMP) process.
BACKGROUND OF THE INVENTION
In semiconductor fabrication integrated circuits and semiconducting devices are formed by sequentially forming features in sequential layers of material in a bottom-up manufacturing method. The manufacturing process utilizes a wide variety of deposition techniques to form the various layered features including various etching techniques such as anisotropic plasma etching to form device feature openings followed by deposition techniques to fill the device features. In order to form reliable devices, close tolerances are required in forming features including photolithographic patterning methods which rely heavily on layer planarization techniques to maintain a proper depth of focus.
Planarization is increasingly important in semiconductor manufacturing techniques. As device sizes decrease, the importance of achieving high resolution features through photolithographic processes correspondingly increases thereby placing more severe constraints on the degree of planarity required of a semiconductor wafer processing surface. Excessive degrees of surface nonplanarity will undesirably affect the quality of several semiconductor manufacturing process including, for example, in a photolithographic process, the positioning the image plane of the process surface within an increasingly limited depth of focus window to achieve high resolution semiconductor feature patterns.
In the formation of conductive interconnections, copper is increasingly used for forming metal interconnects such as vias and trench lines since copper has low resistivity. The undesirable contribution to electrical parasitic effects by metal interconnect residual resistivity has become increasingly important as device sizes have decreased.
One planarization process is chemical mechanical polishing (CMP). CMP is increasingly being used as a planarizing process for semiconductor device layers, especially for applications with smaller semiconductor fabrication processes, for example, below about 0.25 micron. CMP planarization is typically used several different times in the manufacture of a multi-layer semiconductor device, including planarizing a layered device structure in a multi-layer device for subsequent processing of overlying layers. For example, CMP is used to remove excess metal after filling conductive metal interconnects such as vias and trench lines with metal, for example copper, to electrically interconnect the several layers and areas that make up a multi-layer semiconductor device.
In a typical process for forming conductive interconnections in a multi-layer semiconductor device, a damascene process is used to form vias and trench lines for interconnecting different layers and areas of the multilayer device. Vias (e.g., V1, V2 etc. lines) are generally used for vertically electrically interconnecting semiconductor device layers and trench lines (e.g., M1, M2, etc. lines) are used for electrically interconnecting semiconductor device areas within a layer. Vias and trench lines are typically formed as part of a damascene process. Although there are several different methods for forming damascene structures, one typical method generally involves patterning and anisotropically etching a semiconductor feature, for example a via opening within an insulating dielectric layer to make closed communication contact with a conductive area within an underlying layer of the multilayer device. A similar process is then used to pattern and anisotropically etch a trench line opening overlying and encompassing the via opening to form a dual damascene structure. The dual damascene structure is then filled with a metal, for example copper followed by a CMP step to remove excess metal overlying the insulating layer dielectric (ILD) surface and to planarized the ILD surface for a subsequent processing step. The process is then repeated in an overlying ILD layer to form a series of stacked conductive lines which electrically communicate between and within the various layers to form a multi-layered semiconductor device. Typically, vias and dual damascene structures are stacked above one another to reduce an overall space requirement for patterning a semiconductor device.
CMP generally includes placing a process surface of the wafer in contact against a flat polishing surface, imparting a downforce to the wafer backside and moving the wafer and the polishing surface relative to one another. The polishing action is typically aided by a slurry which includes for example, small abrasive particles such as silica (SiO
2
) or alumina (Al
2
O
3
) that abrasively act to remove a portion of the process surface. Additionally, the slurry may include chemicals such as complexing agents and film forming agents that react with the process surface to assist in removing a portion of the surface material, the slurry typically being introduced to contact the wafer surface and the polishing pad.
Typically CMP polishing slurries contain an abrasive material, such as silica or alumina, suspended in an aqueous medium. There are various mechanisms disclosed in the prior art by which metal surfaces can be polished with slurries. In one method, the formation of a thin oxide layer takes place in-situ by reaction between the metal surface and an oxidizing agent which simultaneously forms an oxide layer while an abrasive is removing the oxide layer. The thin abradable oxide layer including the underlying metal layer is thereby selectively removed in a controlled manner by mechanical abrasive action. The rate of material removal can be varied by adjusting the rate of oxide formation and material removal.
Several semiconductor feature defects can be associated with CMP polishing. For example, in CMP polishing metals, for example copper features included in an array of metal interconnects, the copper is removed or eroded at a faster rate than the surrounding field of insulating dielectric. This causes a topography difference between insulating dielectric and the dense copper array, typically referred to as erosion or corrosion. Such erosion (corrosion) can lead to excess removal of copper such that overlying formation of electrical interconnecting features, for example, stacked vias, leads to electrical failure by causing discontinuous electrical communication pathways.
One particular problem related to the formation of copper interconnect features such as copper filled vias and trenches is the practice of forming a conformal barrier/adhesion layer within the anisotropically etched features prior to filling with copper. The barrier/adhesion layer is typically a refractory metal such as tantalum nitride (TaN) formed to prevent diffusion of copper into the porous insulating dielectric layer (ILD) within which the via and trench openings are formed. After filling of the interconnect features with copper, for example by electroplating, a CMP process is carried out to first remove the excess copper overlying the barrier/adhesion layer and another CMP process performed to remove the barrier/adhesion layer overlying the insulating (ILD) layer. During a portion of the CMP processes positively and negatively charges species present in the polishing slurry act as an electrolyte in contact with two dissimilar metals, for example tantalum and copper, thereby forming a galvanic cell. Such galvanic action is believed to be at least in part responsible for copper corrosion at the surface of copper filled features that takes place in CMP processes where both the barrier/adhesion layer and copper features are being polished.
For example, referring to
FIG. 1
is shown a portion of a multi-layer structure including dual damascene structures e.g.,
10
,
12
and
13
,
15
forming stacked dual damascene structures. The stacked dual damascene structures include a via portion e.g.,
10
A,
12
A and a trench line portion e.g

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