Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2000-08-25
2001-09-18
Nguyen, Vinh P. (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S760020
Reexamination Certificate
active
06292006
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuit semiconductor device test apparatus, more particularly to a tester and handler board that provides for multiple site testing.
DESCRIPTION OF THE RELATED ART
Semiconductor device testing systems typically include a tester, which is an expensive piece of computing equipment for generating and receiving test signals, a chip handler, which is an expensive precise robot for moving semiconductor devices from one location to another under control of software, and a docking assembly for aligning and electrically connecting a tester mother board attached to the tester to a handler board attached to the chip handler. Typically, the tester mother board includes a plurality of compressible pins which must be accurately positioned to mate with contact pads or pin openings on the handler board. Sometimes the tester mother board and the handler board are combined, in which case the chip handler inserts semiconductor devices into the single board attached to the tester.
FIG. 1
shows the top view of a segment of a prior art standard automated test equipment (ATE) tester mother board
10
. Mother board
10
includes an inner ring
11
and an outer ring
12
of spaced tester contacts. The rings
11
and
12
of tester contacts include groups of contacts such as groups
11
a
and
12
a
. Each group extends through the board to a male plug on the bottom surface of tester mother board
18
, which is connected to pins of a tester. The tester pins receive signals from a computer. The tester mother board carries signals from the tester mother board to the handler board, and the handler board in turn carries the signals to a device under test. Output signals from the device under test are returned to the tester by a similar path. Tester contact groups
11
a
and
12
a
are repeated radially around the two concentric rings of tester contacts. Each group extends through mother board
10
to form an electrical contact in a plug extending downward from the bottom surface of mother board. These plugs must mate with pins in the tester. Ring
11
is spaced radially from ring
12
by a distanceD, which must match with a corresponding distance in the tester and thus may not be varied. Concentric rings
14
and
15
of compressible pins
14
a
and
15
a
such as pogo pins are provided radially inward of rings
11
and
12
of tester contacts
11
a
and
12
a
. Each of the pogo pins
14
a
and
15
a
is connected to an individual signal line in the tester. A third ring
16
of pogo pins
16
a
are connected to the utility connections of the tester such as the tester's power supplies, relay controls, external +5 volt relay power supply, ground, and board statistics register. (A board statistics register contains information about the board such as its serial number, repair record, model number, and date of manufacture, and can be used by software to verify that the board is acceptable for the current use.) Threaded apertures
17
spaced around the tester mother board allow for connection to a handler board and for alignment of the two boards.
FIG. 2
is a schematic cross-sectional view of tester mother board
10
which shows the groups of tester contacts
11
and
12
, the rings
14
,
15
, and
16
of pogo pins, and metallization lines
19
connecting contacts
11
and
12
to pins
14
,
15
, and
16
. Individual pogo pins
14
a
15
a
,
16
a
and
16
b
are also seen.
FIG. 3
a
illustrates the top surface
209
of a handler board
20
showing via connections
21
to selected pogo pins on the ring
16
of the mating tester mother board
10
, metallization traces such as
22
a
from contact pads such as
20
a
to via connections
21
, traces
22
b
from via connections
21
to contact areas
23
adjacent to a test position
24
into which the semiconductor device will be inserted, mounted, and tested.
FIG. 3
a
also shows a trace
22
c
extending from a contact pad
20
a
to a contact area
23
for holding a device to be tested. Bolts inserted through apertures
26
align handler board
20
with tester mother board
10
of FIG.
1
and hold the two boards together.
FIG. 3
b
is a bottom view of the handler board of
FIG. 3
a
showing contact pads
27
which are contacted by corresponding pogo pins
16
a
of ring
16
and showing the test site
24
for insertion of the semiconductor device under test.
FIG. 3
b
also shows two rings of contact pads
28
and
29
which will be contacted by the pogo pins
14
a
and
14
b
of the two rings
14
and
15
of pogo pins, and shows alignment apertures
26
. Typically, the screws that go through these holes are shoulder bolts to prevent loss during disassembly.
FIG. 4
shows another prior art mother board
30
. Mother board
30
includes a test site
38
for inserting semiconductor devices and thus does not require a separate handler board. In
FIG. 4
, tester contacts
31
are arranged in groups which extend radially toward the center of mother board
30
. A single test site
38
is positioned in the center of mother board
30
for receiving semiconductor devices for testing. The particular test site shown includes 48 sockets
39
for receiving 48 pins of a semiconductor device. Metallization traces connect the tester contacts to the sockets, one metallization trace for connecting each socket to a contact. For example, metallization trace
36
a
connects contact
31
a
to socket
39
a
. In
FIG. 4
, 24 of the metallization traces are shown. Additionally, 24 more traces are formed in interior layers of mother board
30
. Mother board
30
includes many more than 48 contacts
31
. One mother board manufactured by Micro Ceramics, Inc. of Los Gatos, Calif., similar to mother board
30
includes 1152 contacts for interfacing with the SC212 tester from Credence Systems Corporation. Of these 1152 contacts, about half are connected to a ground plane in the board. Ground planes separate layers of metallization from each other. Some contacts are connected to two layers of power planes. Some are also connected to board statistics registers. About 300 contacts are available for carrying signals to a test site. But the space for test sites in such a mother board is limited to about 25% of the board area, and if the metallization traces are all to have equal delay, it is not possible to lay out 300 metallization traces in the area provided or to provide multiple test sites in the small area. Thus a board such as mother board
30
can not take full advantage of the tester with which it must interface.
FIG. 5
illustrates the interface of the tester mother board of
FIG. 1
to an automated handler board or card
20
where the radial interior or central area of the ring
16
of pogo pins
16
a
and
16
b
(two pins shown) delineates a relatively small diameter working area W
1
, in which a semiconductor device
25
can be mounted. This area, which is about 80-120 square centimeters in a typical handler board is so restricted in size that only a single semiconductor device
25
can be accommodated at one time on the handler board
20
. Indeed, the area available for the device to be tested plus the metallization lines leading to the device may be less than 6% of the total area occupied by this prior art tester interface structure. Further, as can be seen in
FIG. 1
, the radial distance between the innermost ring
16
of pogo pins in tester mother board
10
and the group of tester contacts
12
is relatively long, actually about 12-15 cm in a typically utilized Credence, Inc. No. 8256 tester mother board. The prior art placement of the pogo pin rings
14
,
15
and
16
radially inwardly of the groups
11
and
12
of tester contacts also limits the number of spaced pogo pins which can be accommodated around rings
14
,
15
, and
16
since the ring diameters are relatively small e.g., 12 cm for ring
16
in a Credence No. 8256 tester mother board. The above prior art configuration was designed to have the rings of pogo pins
14
,
15
and
16
as close as possible to the semiconductor device test posi
Bever, Esq. Patrick T.
Nguyen Vinh P.
Xilinx , Inc.
Young Edel M.
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