Method for preventing alignment marks from disappearing after ch

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having substrate registration feature

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438462, 257797, H01L 2176

Patent

active

060109459

ABSTRACT:
A method for preventing alignment marks from disappearing after chemical mechanical polishing according to the invention is disclosed. This method, suitable for a substrate on which devices and first alignment marks are already formed, comprise: forming a metal layer on the substrate, thereby forming second alignment marks on the metal layer above the first alignment marks; forming a required metal pattern on the metal layer and removing part of the metal layer on the first alignment marks; forming a first dielectric layer, an etching stop and a second dielectric layer over the substrate, thereby forming third alignment marks, fourth alignment marks and fifth alignment marks on the first dielectric layer, etching stop and second dielectric layer, respectively; performing chemical mechanical polishing, causing the disappearance of the fifth alignment marks; and forming contact windows in the first dielectric layer and clear out windows on the fourth alignment marks to make said fourth alignment marks reappear. Furthermore, the method for preventing alignment marks from disappearing after chemical mechanical polishing according to the invention not only makes the required alignment marks reappear, but also simplifies the semiconductor process, that is, unlike the prior art, no extra photolithography and etching is required in the invention, because the contact windows and clear out windows are formed simultaneously.

REFERENCES:
patent: 5401691 (1995-03-01), Caldwell
patent: 5640053 (1997-06-01), Caldwell
patent: 5801090 (1997-04-01), Wu
patent: 5911108 (1997-01-01), Yen

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