Thermal measuring and testing – Temperature measurement – Combined with diverse art device
Reexamination Certificate
2001-10-31
2003-09-09
Gutierrez, Diego (Department: 2859)
Thermal measuring and testing
Temperature measurement
Combined with diverse art device
C374S001000, C374S102000, C374S149000, C438S014000, C438S016000, C117S008000, C219S497000, C392S416000
Reexamination Certificate
active
06616331
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method for predicting temperature and also relates to a test wafer for use in temperature prediction. More particularly, this invention provides measures to predict more accurately the actual temperature or temperature distribution of a wafer to be loaded into a thermal processing system (e.g., a plasma-enhanced thermal processing system, in particular) for use as part of the equipment for manufacturing semiconductor devices.
A method for predicting the temperature (the actual temperature) of a wafer to be loaded into a thermal processing system, in which the wafer should be subjected to intense heat in a semiconductor device fabrication process, was disclosed in PCT International Publication No. WO 98/57146.
Hereinafter, the wafer temperature predicting method disclosed in this publication will be described with reference to the drawings.
First, as shown in
FIG. 10A
, dopant ions are implanted into a silicon wafer
101
, thereby forming an amorphous layer
110
a
with a thickness t0 in the uppermost part of the silicon wafer
101
. As a result, the silicon wafer
101
now consists of the amorphous layer
101
a
as the uppermost part thereof and a crystalline layer
101
b
as the other part thereof.
Next, as shown in
FIG. 10B
, the silicon wafer
101
including the amorphous layer
101
a
is loaded into a thermal processing system such as a chemical vapor deposition (CVD) system. Then, a silicon dioxide film
102
is deposited over the amorphous layer
101
a
. In the meantime, crystals start to grow epitaxially from the interface between the amorphous and crystalline layers
101
a
and
101
b
, thereby crystallizing the lowermost part of the amorphous layer
101
a
. As a result, the amorphous layer
101
a
has its thickness decreased from its initial thickness t0 to t1. In this case, the thickness of the amorphous layer
101
a
is measured with a spectroscopic ellipsometer. In
FIG. 10B
, the interface between the amorphous and crystalline layers
101
a
and
101
b
, as shown in
FIG. 10A
, not subjected to heat during the deposition of the silicon dioxide film
102
is indicated as the broken line drawn in the crystalline layer
101
b.
Then, the decrease in thickness of the amorphous layer
101
a
per unit time, i.e., the rate R at which that part of the amorphous layer
101
a
recovers from the amorphous state to crystalline state, is calculated by
R=|t
1
−t
0|/
a
where the thermal processing is supposed to have been performed for a period of time a (s) and 0≦t1≦t0.
It is believed that if the recovery rate R given by this equation is applied to the graph shown in
FIG. 11
, the actual temperature of a silicon wafer to be processed can be predicted. The graph shown in
FIG. 11
illustrates a relationship between the recovery rate R and the temperature T and was drawn after J. Appl. Phys. Vol. 48, No. 10 (1997), p. 4234. It should be noted that the amorphous layer
101
a
may be formed by implanting arsenic (As) ions into the wafer
101
.
The present inventors carried out various experiments on the known method for predicting a wafer temperature. As a result, we found that the actual wafer temperature could not be predicted accurately enough by the known method when the method was applied to a thermal processing system for a relatively low-temperature process (e.g., plasma CVD or plasma etching process).
This is because the uppermost part of the amorphous layer
101
a
in the silicon wafer
101
is unintentionally oxidized by an oxygen plasma in the process step shown in FIG.
10
B. That is to say, the amorphous layer
101
a
is not thinned just because the lowermost part of the amorphous layer
101
a
is crystallized around the interface with the crystalline layer
101
b
by heat treatment in the thermal processing system. In addition, the uppermost part of the amorphous layer
101
a
is oxidized and thus disappears through the plasma processing.
As a result, that part of the amorphous layer
101
a
, which is supposed to have recovered to the crystalline state through the crystallization alone, has a thickness greater than expected. Accordingly, the resultant recovery thickness (t0−t1) or recovery rate R increases excessively. Thus, the rate R of recovery from the amorphous to the crystalline state cannot be accurately obtained. Consequently, the actual temperature of a silicon wafer to be processed cannot be predicted accurately.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to predict more accurately the actual temperature or temperature distribution of a wafer subjected to heat in a thermal processing system for a relatively low-temperature process, e.g., plasma-enhanced thermal processing system.
In order to achieve this object, according to the present invention, a test wafer for use in temperature prediction includes a protective film for protecting an amorphous layer.
Specifically, an inventive method is for predicting, using a test wafer, a temperature of a wafer to be loaded into a device fabrication system that generates heat. The method includes the steps of: a) preparing the test wafer, which includes a first semiconductor layer formed in a crystalline state, a second semiconductor layer formed in an amorphous state on the first semiconductor layer, and a protective film formed over the second semiconductor layer; b) loading the test wafer into the device fabrication system and then heating the test wafer for a predetermined period of time in the device fabrication system; c) calculating a recovery rate at which part of the second semiconductor layer that has been heated recovers from the amorphous state to the crystalline state at the interface with the first semiconductor layer; and d) measuring a temperature of the test wafer that has been heated, according to a relationship between the recovery rate and a temperature corresponding to the recovery rate.
According to the inventive method, a protective film is formed over a second semiconductor layer, and thus the surface of the second semiconductor layer is not exposed directly to a plasma. Therefore, decrease in thickness of the second semiconductor layer due to oxidation of the uppermost part thereof can be prevented. Thus, a recovery rate for obtaining the actual temperature of a wafer can be calculated more accurately by the thickness of the second semiconductor layer subjected to heat. As a result, the actual temperature of a wafer to be loaded into a device fabrication system can also be predicted more accurately.
In one embodiment of the present invention, the first and second semiconductor layers may be made of silicon and the protective film may be made of silicon dioxide.
In another embodiment, the test wafer may include a conductive coating, which has been formed over the protective film and contains a metal. If the thermal system used in this embodiment is also used for depositing a film, it is necessary to remove the deposited film so as to measure the thickness of the second semiconductor layer. In this case, if the deposited film has a small etch selectivity with respect to the protective film, the protective film is unintentionally removed simultaneously with the deposited film. Then, the second semiconductor layer acts as an etch stopper layer practically. As a result, after the protective film has been removed, the uppermost part of the second semiconductor layer is damaged. However, if a conductive coating that contains a metal is provided over the protective film, only the deposited film can be removed irrespective of the etch selectivity between the deposited film and the protective film. As a result, the second semiconductor layer will not be damaged.
In still another embodiment, the recovery rate may be calculated by dividing a decrease in thickness of the second semiconductor layer by the predetermined period of time.
In yet another embodiment, the step a) may include the step of measuring a thickness of the second semiconductor layer to obtain an initia
Nambu Yuko
Shibata Satoshi
Costellia Jeffrey L.
Gutierrez Diego
Matsushita Electric Industrial Co. LTD
Nixon & Peabody LLP
Pruchnic Jr. Stanley J.
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