Boots – shoes – and leggings
Patent
1993-07-09
1994-03-15
Harvey, Jack B.
Boots, shoes, and leggings
364488, 364490, G06F 1560
Patent
active
052950883
ABSTRACT:
A method estimates the interconnect capacitance of a first net in an integrated circuit. The first step of the method includes the generation of a value which indicates how tightly connected to one another are components connected to the first net. The second step of the method includes the prediction of interconnect capacitance of the first net based on the value generated in the first step and a number representing how many components are connected to the first net.
REFERENCES:
patent: 4763289 (1988-08-01), Barzilai et al.
patent: 4815024 (1989-03-01), Lewis
patent: 5107320 (1992-04-01), Iranmanesh
Kortekaas; "On-Chip Quasi-static Floating-gate Capacitance Measurement Method"; IEEE Conf on Microelectronics; Mar. 1990.
Hartoog Mark R.
Shur Robert D.
Harvey Jack B.
Ramirez Ellis B.
VLSI Technology Inc.
Weller Douglas L.
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